Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	73934832	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	80831195	1		T1	266674		T2	332811		T3	290151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	148887456	1		T1	533971		T2	665463		T3	85429
values[0x0]	2792177	1		T1	17		T2	143		T3	108237
values[0x1]	3086394	1		T1	25		T2	176		T3	120097

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58917753	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	95848274	1		T1	320274		T2	399615		T3	301595

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	491761	1		T1	2042		T2	25640		T3	1141
valid_sources[0x01]	635883	1		T1	2058		T2	26510		T3	1258
valid_sources[0x02]	497019	1		T1	2078		T2	26063		T3	1244
valid_sources[0x03]	488386	1		T1	2154		T2	26080		T3	1142
valid_sources[0x04]	490072	1		T1	2042		T2	25863		T3	1125
valid_sources[0x05]	487056	1		T1	2118		T2	25781		T3	1256
valid_sources[0x06]	487091	1		T1	2054		T2	25873		T3	1346
valid_sources[0x07]	498388	1		T1	2229		T2	25852		T3	1151
valid_sources[0x08]	580856	1		T1	2086		T2	26260		T3	1185
valid_sources[0x09]	496222	1		T1	2091		T2	26183		T3	1091
valid_sources[0x0a]	528085	1		T1	2123		T2	26121		T3	1222
valid_sources[0x0b]	492986	1		T1	2127		T2	26254		T3	1303
valid_sources[0x0c]	490466	1		T1	2024		T2	25869		T3	1292
valid_sources[0x0d]	492917	1		T1	2098		T2	25726		T3	1192
valid_sources[0x0e]	491816	1		T1	2089		T2	25813		T3	1234
valid_sources[0x0f]	491774	1		T1	2099		T2	26060		T3	1228
valid_sources[0x10]	1469098	1		T1	2030		T2	26179		T3	1234
valid_sources[0x11]	496497	1		T1	1989		T2	26259		T3	1156
valid_sources[0x12]	492042	1		T1	2008		T2	25726		T3	1291
valid_sources[0x13]	561407	1		T1	1977		T2	25913		T3	1213
valid_sources[0x14]	524882	1		T1	2081		T2	25979		T3	1173
valid_sources[0x15]	498823	1		T1	2089		T2	25752		T3	1237
valid_sources[0x16]	486320	1		T1	2112		T2	26308		T3	1205
valid_sources[0x17]	490693	1		T1	2082		T2	25765		T3	1287
valid_sources[0x18]	501704	1		T1	2045		T2	26049		T3	1220
valid_sources[0x19]	497631	1		T1	2023		T2	25707		T3	1294
valid_sources[0x1a]	491175	1		T1	2146		T2	26123		T3	1283
valid_sources[0x1b]	494728	1		T1	2079		T2	26153		T3	1220
valid_sources[0x1c]	488313	1		T1	2119		T2	26027		T3	1293
valid_sources[0x1d]	492312	1		T1	2040		T2	26115		T3	1241
valid_sources[0x1e]	492567	1		T1	2179		T2	25778		T3	1181
valid_sources[0x1f]	485423	1		T1	2078		T2	25718		T3	1196
valid_sources[0x20]	488758	1		T1	2077		T2	26119		T3	1183
valid_sources[0x21]	491295	1		T1	2065		T2	26088		T3	1189
valid_sources[0x22]	490064	1		T1	2081		T2	25671		T3	1326
valid_sources[0x23]	540557	1		T1	2065		T2	26104		T3	1252
valid_sources[0x24]	493359	1		T1	2119		T2	25578		T3	1127
valid_sources[0x25]	502796	1		T1	2200		T2	25893		T3	1198
valid_sources[0x26]	810684	1		T1	2215		T2	26549		T3	1203
valid_sources[0x27]	488875	1		T1	2093		T2	26188		T3	1261
valid_sources[0x28]	491090	1		T1	2075		T2	26204		T3	1295
valid_sources[0x29]	490200	1		T1	1997		T2	25845		T3	1241
valid_sources[0x2a]	490370	1		T1	2211		T2	26149		T3	1203
valid_sources[0x2b]	492371	1		T1	2118		T2	25695		T3	1280
valid_sources[0x2c]	493000	1		T1	2144		T2	26229		T3	1284
valid_sources[0x2d]	495350	1		T1	2113		T2	25850		T3	1228
valid_sources[0x2e]	682162	1		T1	2105		T2	26025		T3	1239
valid_sources[0x2f]	552928	1		T1	2071		T2	25826		T3	1280
valid_sources[0x30]	486374	1		T1	2078		T2	25828		T3	1347
valid_sources[0x31]	489869	1		T1	2090		T2	26155		T3	1256
valid_sources[0x32]	489355	1		T1	2071		T2	25923		T3	1301
valid_sources[0x33]	488229	1		T1	1995		T2	25620		T3	1168
valid_sources[0x34]	554339	1		T1	2090		T2	26192		T3	1263
valid_sources[0x35]	538485	1		T1	2109		T2	25857		T3	1108
valid_sources[0x36]	489414	1		T1	2059		T2	25913		T3	1098
valid_sources[0x37]	489487	1		T1	2104		T2	25669		T3	1163
valid_sources[0x38]	490342	1		T1	2151		T2	26121		T3	1180
valid_sources[0x39]	492132	1		T1	2221		T2	26031		T3	1347
valid_sources[0x3a]	492740	1		T1	2058		T2	25731		T3	1173
valid_sources[0x3b]	493889	1		T1	2041		T2	26293		T3	1184
valid_sources[0x3c]	494081	1		T1	2140		T2	26035		T3	1176
valid_sources[0x3d]	492308	1		T1	1986		T2	25928		T3	1301
valid_sources[0x3e]	492887	1		T1	2071		T2	25763		T3	1202
valid_sources[0x3f]	493918	1		T1	2070		T2	25676		T3	1272
valid_sources[0x40]	490095	1		T1	2110		T2	25848		T3	1260
valid_sources[0x41]	492641	1		T1	2191		T2	25933		T3	1376
valid_sources[0x42]	512729	1		T1	2025		T2	26180		T3	1244
valid_sources[0x43]	492770	1		T1	2014		T2	26425		T3	1084
valid_sources[0x44]	491492	1		T1	2150		T2	25708		T3	1186
valid_sources[0x45]	493888	1		T1	2153		T2	25913		T3	1245
valid_sources[0x46]	497102	1		T1	2009		T2	25969		T3	1128
valid_sources[0x47]	510879	1		T1	2035		T2	25981		T3	1188
valid_sources[0x48]	496030	1		T1	2047		T2	25890		T3	1135
valid_sources[0x49]	491926	1		T1	1945		T2	25837		T3	1104
valid_sources[0x4a]	491730	1		T1	2158		T2	26384		T3	1279
valid_sources[0x4b]	490622	1		T1	2073		T2	25741		T3	1169
valid_sources[0x4c]	493069	1		T1	2020		T2	25975		T3	1259
valid_sources[0x4d]	2018665	1		T1	2166		T2	26143		T3	1152
valid_sources[0x4e]	549883	1		T1	2021		T2	25732		T3	1268
valid_sources[0x4f]	498086	1		T1	2105		T2	26128		T3	1307
valid_sources[0x50]	507142	1		T1	2048		T2	26264		T3	1316
valid_sources[0x51]	490766	1		T1	2116		T2	25845		T3	1239
valid_sources[0x52]	488896	1		T1	2073		T2	25773		T3	1142
valid_sources[0x53]	495090	1		T1	2113		T2	25938		T3	1260
valid_sources[0x54]	491306	1		T1	2127		T2	26041		T3	1226
valid_sources[0x55]	1075918	1		T1	2080		T2	26050		T3	1208
valid_sources[0x56]	497178	1		T1	2072		T2	26056		T3	1246
valid_sources[0x57]	494949	1		T1	2120		T2	26145		T3	1292
valid_sources[0x58]	568106	1		T1	2118		T2	26261		T3	1105
valid_sources[0x59]	492567	1		T1	2195		T2	26269		T3	1074
valid_sources[0x5a]	492608	1		T1	2082		T2	26003		T3	1175
valid_sources[0x5b]	490183	1		T1	2068		T2	26041		T3	1251
valid_sources[0x5c]	493534	1		T1	2107		T2	25870		T3	1197
valid_sources[0x5d]	493086	1		T1	2065		T2	26371		T3	1245
valid_sources[0x5e]	522771	1		T1	2037		T2	26112		T3	1238
valid_sources[0x5f]	491814	1		T1	2096		T2	27072		T3	1246
valid_sources[0x60]	496824	1		T1	1990		T2	26405		T3	1304
valid_sources[0x61]	490951	1		T1	2018		T2	25737		T3	1252
valid_sources[0x62]	488413	1		T1	2093		T2	25838		T3	1233
valid_sources[0x63]	1413014	1		T1	1997		T2	26527		T3	1175
valid_sources[0x64]	492582	1		T1	2145		T2	25852		T3	1197
valid_sources[0x65]	560920	1		T1	2043		T2	26355		T3	1330
valid_sources[0x66]	486554	1		T1	2070		T2	26081		T3	1259
valid_sources[0x67]	490823	1		T1	2162		T2	25680		T3	1189
valid_sources[0x68]	604872	1		T1	2127		T2	25520		T3	1293
valid_sources[0x69]	612084	1		T1	1966		T2	25702		T3	1195
valid_sources[0x6a]	499706	1		T1	2116		T2	25616		T3	1235
valid_sources[0x6b]	2831180	1		T1	2017		T2	25766		T3	1252
valid_sources[0x6c]	484405	1		T1	1978		T2	25956		T3	1165
valid_sources[0x6d]	493541	1		T1	1957		T2	26121		T3	1243
valid_sources[0x6e]	491317	1		T1	2148		T2	25916		T3	1213
valid_sources[0x6f]	487429	1		T1	2110		T2	26204		T3	1079
valid_sources[0x70]	544017	1		T1	2191		T2	25980		T3	1199
valid_sources[0x71]	488615	1		T1	2043		T2	26223		T3	1170
valid_sources[0x72]	490271	1		T1	2046		T2	25575		T3	1271
valid_sources[0x73]	505588	1		T1	1989		T2	26394		T3	1234
valid_sources[0x74]	494750	1		T1	2161		T2	26331		T3	1355
valid_sources[0x75]	491071	1		T1	2181		T2	26202		T3	1114
valid_sources[0x76]	488095	1		T1	2057		T2	25919		T3	1142
valid_sources[0x77]	2304277	1		T1	2034		T2	26072		T3	1275
valid_sources[0x78]	1030234	1		T1	2101		T2	25698		T3	1225
valid_sources[0x79]	591201	1		T1	2049		T2	26097		T3	1161
valid_sources[0x7a]	488230	1		T1	1966		T2	25744		T3	1293
valid_sources[0x7b]	490751	1		T1	2045		T2	26066		T3	1278
valid_sources[0x7c]	1657006	1		T1	2138		T2	25942		T3	1203
valid_sources[0x7d]	492655	1		T1	2139		T2	26351		T3	1306
valid_sources[0x7e]	490196	1		T1	2070		T2	25852		T3	1277
valid_sources[0x7f]	488020	1		T1	2213		T2	26098		T3	1261
valid_sources[0x80]	495469	1		T1	2063		T2	26243		T3	1212

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75322150

1

T1

266639

T2

332789

T3

76442

values[0x0]

all_enables

biggest_size

2754946

1

T1

17

T2

103

T3

106949

values[0x1]

all_enables

biggest_size

2754099

1

T1

18

T2

112

T3

106760