Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	9726177	0	0
cfg0_rd_A	2147483647	27005	0	0
compare_lower0_0_rd_A	2147483647	30746	0	0
compare_upper0_0_rd_A	2147483647	26707	0	0
ctrl_rd_A	2147483647	27785	0	0
intr_enable0_rd_A	2147483647	33380	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9726177	0	0
T3	128150	388032	0	0
T4	149569	0	0	0
T5	100153	0	0	0
T6	131187	0	0	0
T7	740841	0	0	0
T8	204642	0	0	0
T9	368559	0	0	0
T10	295451	0	0	0
T11	142545	0	0	0
T12	0	94604	0	0
T13	0	305785	0	0
T31	0	9	0	0
T32	0	10	0	0
T34	0	188888	0	0
T35	0	789	0	0
T36	0	167	0	0
T37	0	232	0	0
T38	0	891	0	0
T39	312873	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27005	0	0
T12	381098	999	0	0
T13	108731	0	0	0
T16	2618	31	0	0
T32	0	112	0	0
T33	0	23	0	0
T34	864304	1898	0	0
T40	0	8	0	0
T41	0	35	0	0
T42	0	8	0	0
T43	0	9	0	0
T44	0	105	0	0
T45	134006	0	0	0
T46	535969	0	0	0
T47	355622	0	0	0
T48	124542	0	0	0
T49	768582	0	0	0
T50	10679	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30746	0	0
T12	381098	1183	0	0
T13	108731	0	0	0
T16	2618	10	0	0
T32	0	61	0	0
T33	0	17	0	0
T34	864304	2212	0	0
T41	0	4	0	0
T42	0	4	0	0
T43	0	17	0	0
T44	0	126	0	0
T45	134006	0	0	0
T46	535969	0	0	0
T47	355622	0	0	0
T48	124542	0	0	0
T49	768582	0	0	0
T50	10679	0	0	0
T51	0	8	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	26707	0	0
T12	381098	1053	0	0
T13	108731	0	0	0
T16	2618	32	0	0
T32	0	81	0	0
T33	0	33	0	0
T34	864304	2203	0	0
T40	0	2	0	0
T41	0	13	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	114	0	0
T45	134006	0	0	0
T46	535969	0	0	0
T47	355622	0	0	0
T48	124542	0	0	0
T49	768582	0	0	0
T50	10679	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27785	0	0
T12	381098	940	0	0
T13	108731	0	0	0
T16	2618	37	0	0
T32	0	67	0	0
T33	0	26	0	0
T34	864304	2096	0	0
T40	0	4	0	0
T41	0	33	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	147	0	0
T45	134006	0	0	0
T46	535969	0	0	0
T47	355622	0	0	0
T48	124542	0	0	0
T49	768582	0	0	0
T50	10679	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33380	0	0
T8	204642	46	0	0
T9	368559	0	0	0
T10	295451	0	0	0
T11	142545	0	0	0
T12	381098	1280	0	0
T16	0	30	0	0
T34	0	2634	0	0
T39	312873	0	0	0
T40	0	7	0	0
T45	134006	0	0	0
T46	535969	0	0	0
T47	355622	0	0	0
T48	124542	0	0	0
T52	0	33	0	0
T53	0	37	0	0
T54	0	31	0	0
T55	0	39	0	0
T56	0	12	0	0