Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	11010854	0	0
cfg0_rd_A	2147483647	27345	0	0
compare_lower0_0_rd_A	2147483647	30794	0	0
compare_upper0_0_rd_A	2147483647	27988	0	0
ctrl_rd_A	2147483647	27323	0	0
intr_enable0_rd_A	2147483647	33600	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11010854	0	0
T1	647738	220257	0	0
T2	111321	0	0	0
T3	416315	0	0	0
T4	281607	0	0	0
T5	156061	0	0	0
T6	773601	0	0	0
T7	463257	0	0	0
T8	109523	0	0	0
T9	120487	0	0	0
T10	464120	0	0	0
T13	0	420560	0	0
T14	0	254996	0	0
T16	0	242	0	0
T36	0	77574	0	0
T37	0	251426	0	0
T38	0	19907	0	0
T39	0	207515	0	0
T40	0	339	0	0
T41	0	664	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27345	0	0
T35	0	7	0	0
T36	321402	678	0	0
T37	0	1400	0	0
T38	0	176	0	0
T42	0	5	0	0
T43	0	6	0	0
T44	0	40	0	0
T45	0	15	0	0
T46	0	15	0	0
T47	0	74	0	0
T48	300783	0	0	0
T49	230289	0	0	0
T50	609325	0	0	0
T51	308830	0	0	0
T52	875978	0	0	0
T53	382798	0	0	0
T54	103144	0	0	0
T55	131742	0	0	0
T56	368720	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30794	0	0
T35	0	6	0	0
T36	321402	875	0	0
T37	0	1595	0	0
T38	0	212	0	0
T42	0	17	0	0
T44	0	95	0	0
T45	0	30	0	0
T46	0	8	0	0
T47	0	13	0	0
T48	300783	0	0	0
T49	230289	0	0	0
T50	609325	0	0	0
T51	308830	0	0	0
T52	875978	0	0	0
T53	382798	0	0	0
T54	103144	0	0	0
T55	131742	0	0	0
T56	368720	0	0	0
T57	0	18	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27988	0	0
T35	0	11	0	0
T36	321402	1044	0	0
T37	0	1328	0	0
T38	0	251	0	0
T42	0	43	0	0
T43	0	4	0	0
T44	0	49	0	0
T45	0	25	0	0
T46	0	8	0	0
T48	300783	0	0	0
T49	230289	0	0	0
T50	609325	0	0	0
T51	308830	0	0	0
T52	875978	0	0	0
T53	382798	0	0	0
T54	103144	0	0	0
T55	131742	0	0	0
T56	368720	0	0	0
T57	0	19	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27323	0	0
T36	321402	772	0	0
T37	0	1387	0	0
T38	0	257	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	57	0	0
T45	0	65	0	0
T46	0	1	0	0
T47	0	35	0	0
T48	300783	0	0	0
T49	230289	0	0	0
T50	609325	0	0	0
T51	308830	0	0	0
T52	875978	0	0	0
T53	382798	0	0	0
T54	103144	0	0	0
T55	131742	0	0	0
T56	368720	0	0	0
T57	0	5	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33600	0	0
T35	0	8	0	0
T36	321402	1214	0	0
T37	0	1795	0	0
T38	0	204	0	0
T42	0	39	0	0
T43	0	4	0	0
T48	300783	0	0	0
T49	230289	0	0	0
T50	609325	0	0	0
T51	308830	0	0	0
T52	875978	0	0	0
T53	382798	0	0	0
T54	103144	0	0	0
T55	131742	0	0	0
T56	368720	0	0	0
T57	0	6	0	0
T58	0	19	0	0
T59	0	30	0	0
T60	0	13	0	0