Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	4443268	0	0
cfg0_rd_A	2147483647	13840	0	0
compare_lower0_0_rd_A	2147483647	15641	0	0
compare_upper0_0_rd_A	2147483647	14072	0	0
ctrl_rd_A	2147483647	14029	0	0
intr_enable0_rd_A	2147483647	17826	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4443268	0	0
T11	381500	158066	0	0
T12	0	54544	0	0
T13	0	69416	0	0
T32	0	32251	0	0
T33	0	147598	0	0
T34	0	227997	0	0
T35	0	130908	0	0
T36	0	125821	0	0
T37	0	351350	0	0
T38	0	176353	0	0
T39	119694	0	0	0
T40	801630	0	0	0
T41	142012	0	0	0
T42	139421	0	0	0
T43	946479	0	0	0
T44	844347	0	0	0
T45	213628	0	0	0
T46	149863	0	0	0
T47	599341	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13840	0	0
T12	190373	304	0	0
T13	515998	670	0	0
T32	121806	269	0	0
T34	0	2382	0	0
T48	0	896	0	0
T49	0	3325	0	0
T50	0	406	0	0
T51	0	545	0	0
T52	0	2090	0	0
T53	0	658	0	0
T54	120468	0	0	0
T55	140163	0	0	0
T56	948762	0	0	0
T57	166334	0	0	0
T58	551189	0	0	0
T59	532429	0	0	0
T60	751616	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15641	0	0
T12	190373	292	0	0
T13	515998	682	0	0
T32	121806	368	0	0
T34	0	2671	0	0
T48	0	1015	0	0
T49	0	4135	0	0
T50	0	368	0	0
T51	0	569	0	0
T52	0	2439	0	0
T53	0	775	0	0
T54	120468	0	0	0
T55	140163	0	0	0
T56	948762	0	0	0
T57	166334	0	0	0
T58	551189	0	0	0
T59	532429	0	0	0
T60	751616	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14072	0	0
T12	190373	409	0	0
T13	515998	705	0	0
T32	121806	323	0	0
T34	0	2361	0	0
T48	0	992	0	0
T49	0	3453	0	0
T50	0	449	0	0
T51	0	445	0	0
T52	0	2200	0	0
T53	0	708	0	0
T54	120468	0	0	0
T55	140163	0	0	0
T56	948762	0	0	0
T57	166334	0	0	0
T58	551189	0	0	0
T59	532429	0	0	0
T60	751616	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14029	0	0
T12	190373	313	0	0
T13	515998	627	0	0
T32	121806	293	0	0
T34	0	2503	0	0
T48	0	873	0	0
T49	0	3501	0	0
T50	0	422	0	0
T51	0	555	0	0
T52	0	2119	0	0
T53	0	687	0	0
T54	120468	0	0	0
T55	140163	0	0	0
T56	948762	0	0	0
T57	166334	0	0	0
T58	551189	0	0	0
T59	532429	0	0	0
T60	751616	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17826	0	0
T12	0	412	0	0
T13	0	968	0	0
T19	266203	22	0	0
T20	161863	0	0	0
T21	130667	0	0	0
T22	477127	0	0	0
T23	7779	0	0	0
T24	469870	0	0	0
T25	176148	9	0	0
T26	189237	0	0	0
T27	538506	0	0	0
T32	0	416	0	0
T34	0	2698	0	0
T48	0	1037	0	0
T61	0	27	0	0
T62	0	80	0	0
T63	0	47	0	0
T64	102783	0	0	0