Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53198809	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	54637175	1		T1	147397		T3	3904		T4	30306

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	106586108	1		T1	294102		T2	1		T3	7714
values[0x0]	593346	1		T1	85		T3	13		T4	8
values[0x1]	656530	1		T1	74		T3	12		T4	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42476309	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	65359675	1		T1	176804		T2	1		T3	4688

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	306846	1		T1	1135		T6	1947		T7	35
valid_sources[0x01]	308659	1		T1	1112		T6	1787		T7	40
valid_sources[0x02]	310127	1		T1	1111		T6	1811		T7	40
valid_sources[0x03]	307780	1		T1	1074		T6	1749		T7	34
valid_sources[0x04]	307318	1		T1	1138		T6	1712		T7	49
valid_sources[0x05]	307511	1		T1	1147		T6	1766		T7	36
valid_sources[0x06]	310090	1		T1	1137		T6	1884		T7	46
valid_sources[0x07]	307615	1		T1	1138		T6	1897		T7	43
valid_sources[0x08]	328061	1		T1	1209		T6	1850		T7	52
valid_sources[0x09]	964299	1		T1	1121		T6	1772		T7	46
valid_sources[0x0a]	308314	1		T1	1109		T6	1703		T7	42
valid_sources[0x0b]	309330	1		T1	1204		T6	1690		T7	40
valid_sources[0x0c]	307653	1		T1	1178		T6	1780		T7	35
valid_sources[0x0d]	307802	1		T1	1111		T6	1881		T7	48
valid_sources[0x0e]	309582	1		T1	1133		T6	1721		T7	41
valid_sources[0x0f]	303248	1		T1	1141		T6	1847		T7	41
valid_sources[0x10]	2038147	1		T1	1123		T6	1874		T7	36
valid_sources[0x11]	307376	1		T1	1176		T6	1737		T7	41
valid_sources[0x12]	305822	1		T1	1088		T6	1815		T7	45
valid_sources[0x13]	307357	1		T1	1200		T6	1803		T7	46
valid_sources[0x14]	527330	1		T1	1147		T6	1644		T7	36
valid_sources[0x15]	311738	1		T1	1184		T6	1851		T7	33
valid_sources[0x16]	304306	1		T1	1103		T6	1738		T7	38
valid_sources[0x17]	1315914	1		T1	1152		T6	1660		T7	32
valid_sources[0x18]	306565	1		T1	1175		T6	1788		T7	48
valid_sources[0x19]	310094	1		T1	1127		T6	1750		T7	38
valid_sources[0x1a]	308566	1		T1	1201		T6	1860		T7	42
valid_sources[0x1b]	311707	1		T1	1105		T6	1799		T7	44
valid_sources[0x1c]	765571	1		T1	1169		T6	1917		T7	50
valid_sources[0x1d]	308806	1		T1	1151		T6	1841		T7	56
valid_sources[0x1e]	306718	1		T1	1116		T6	1774		T7	49
valid_sources[0x1f]	450900	1		T1	1170		T6	1807		T7	50
valid_sources[0x20]	308599	1		T1	1145		T6	1842		T7	38
valid_sources[0x21]	307261	1		T1	1152		T6	1756		T7	35
valid_sources[0x22]	307416	1		T1	1170		T6	1899		T7	47
valid_sources[0x23]	310083	1		T1	1138		T2	1		T6	1859
valid_sources[0x24]	308009	1		T1	1230		T6	1909		T7	34
valid_sources[0x25]	682503	1		T1	1106		T6	1833		T7	31
valid_sources[0x26]	310202	1		T1	1155		T6	1744		T7	41
valid_sources[0x27]	308399	1		T1	1132		T6	1667		T7	51
valid_sources[0x28]	310050	1		T1	1125		T6	1784		T7	38
valid_sources[0x29]	308451	1		T1	1178		T6	1648		T7	33
valid_sources[0x2a]	305897	1		T1	1243		T6	1792		T7	46
valid_sources[0x2b]	306442	1		T1	1152		T6	1660		T7	37
valid_sources[0x2c]	660357	1		T1	1202		T6	1849		T7	46
valid_sources[0x2d]	308794	1		T1	1170		T6	1772		T7	37
valid_sources[0x2e]	306778	1		T1	1216		T6	1798		T7	45
valid_sources[0x2f]	309561	1		T1	1083		T6	1803		T7	50
valid_sources[0x30]	306331	1		T1	1130		T6	1791		T7	49
valid_sources[0x31]	308663	1		T1	1105		T6	1663		T7	56
valid_sources[0x32]	6360149	1		T1	1222		T6	1791		T7	39
valid_sources[0x33]	305585	1		T1	1157		T6	1879		T7	48
valid_sources[0x34]	524916	1		T1	1165		T6	1828		T7	47
valid_sources[0x35]	307728	1		T1	1104		T6	1955		T7	54
valid_sources[0x36]	308967	1		T1	1160		T6	1776		T7	42
valid_sources[0x37]	309359	1		T1	1147		T6	1797		T7	30
valid_sources[0x38]	309798	1		T1	1215		T6	2044		T7	45
valid_sources[0x39]	944587	1		T1	1213		T6	1831		T7	50
valid_sources[0x3a]	578845	1		T1	1045		T6	1681		T7	51
valid_sources[0x3b]	309149	1		T1	1148		T6	1952		T7	29
valid_sources[0x3c]	306889	1		T1	1145		T6	1812		T7	29
valid_sources[0x3d]	308941	1		T1	1104		T6	1938		T7	43
valid_sources[0x3e]	309713	1		T1	1126		T6	1698		T7	27
valid_sources[0x3f]	318386	1		T1	1128		T6	1828		T7	43
valid_sources[0x40]	305818	1		T1	1113		T6	1715		T7	37
valid_sources[0x41]	306004	1		T1	1123		T6	1738		T7	38
valid_sources[0x42]	309508	1		T1	1233		T6	1767		T7	42
valid_sources[0x43]	306586	1		T1	1120		T6	1765		T7	40
valid_sources[0x44]	313427	1		T1	1093		T6	1804		T7	37
valid_sources[0x45]	307491	1		T1	1166		T6	1655		T7	47
valid_sources[0x46]	681081	1		T1	1174		T6	1789		T7	35
valid_sources[0x47]	304874	1		T1	1119		T6	1854		T7	38
valid_sources[0x48]	324983	1		T1	1174		T6	1819		T7	51
valid_sources[0x49]	310195	1		T1	1134		T6	1799		T7	37
valid_sources[0x4a]	310536	1		T1	1239		T6	1828		T7	54
valid_sources[0x4b]	425391	1		T1	1133		T6	1755		T7	41
valid_sources[0x4c]	312548	1		T1	1125		T5	5606		T6	1891
valid_sources[0x4d]	658911	1		T1	1106		T6	1862		T7	44
valid_sources[0x4e]	310734	1		T1	1158		T6	1753		T7	39
valid_sources[0x4f]	309006	1		T1	1131		T6	1763		T7	42
valid_sources[0x50]	307295	1		T1	1226		T6	1682		T7	36
valid_sources[0x51]	1969128	1		T1	1192		T6	1784		T7	39
valid_sources[0x52]	309641	1		T1	1093		T6	1821		T7	45
valid_sources[0x53]	307357	1		T1	1145		T6	1837		T7	44
valid_sources[0x54]	478105	1		T1	1183		T6	1849		T7	42
valid_sources[0x55]	309175	1		T1	1106		T6	1894		T7	46
valid_sources[0x56]	308175	1		T1	1225		T6	1785		T7	54
valid_sources[0x57]	306423	1		T1	1105		T6	1806		T7	35
valid_sources[0x58]	1287057	1		T1	1144		T6	1919		T7	35
valid_sources[0x59]	307963	1		T1	1143		T6	1886		T7	35
valid_sources[0x5a]	307465	1		T1	1115		T6	1818		T7	37
valid_sources[0x5b]	305822	1		T1	1171		T6	1934		T7	34
valid_sources[0x5c]	711211	1		T1	1143		T6	1931		T7	44
valid_sources[0x5d]	309679	1		T1	1114		T6	1584		T7	44
valid_sources[0x5e]	310188	1		T1	1175		T6	1724		T7	36
valid_sources[0x5f]	307240	1		T1	1123		T6	1815		T7	35
valid_sources[0x60]	304191	1		T1	1127		T6	1866		T7	40
valid_sources[0x61]	911832	1		T1	1204		T6	1891		T7	49
valid_sources[0x62]	305963	1		T1	1119		T6	1869		T7	41
valid_sources[0x63]	375148	1		T1	1199		T6	1857		T7	43
valid_sources[0x64]	316825	1		T1	1114		T6	1912		T7	43
valid_sources[0x65]	306039	1		T1	1126		T6	1801		T7	35
valid_sources[0x66]	336159	1		T1	1220		T6	1861		T7	43
valid_sources[0x67]	307786	1		T1	1185		T6	1838		T7	43
valid_sources[0x68]	468721	1		T1	1131		T6	1856		T7	39
valid_sources[0x69]	309681	1		T1	1146		T6	1820		T7	51
valid_sources[0x6a]	311912	1		T1	1208		T6	1664		T7	45
valid_sources[0x6b]	1294227	1		T1	1184		T6	1673		T7	46
valid_sources[0x6c]	311380	1		T1	1145		T6	1807		T7	43
valid_sources[0x6d]	303714	1		T1	1131		T6	1893		T7	35
valid_sources[0x6e]	308128	1		T1	1151		T6	1735		T7	40
valid_sources[0x6f]	309576	1		T1	1122		T6	1922		T7	43
valid_sources[0x70]	305755	1		T1	1108		T6	1708		T7	39
valid_sources[0x71]	307318	1		T1	1154		T6	1827		T7	41
valid_sources[0x72]	308329	1		T1	1188		T6	1722		T7	50
valid_sources[0x73]	653818	1		T1	1126		T6	1779		T7	49
valid_sources[0x74]	309811	1		T1	1170		T6	1788		T7	30
valid_sources[0x75]	308576	1		T1	1183		T6	2028		T7	34
valid_sources[0x76]	322103	1		T1	1126		T6	1948		T7	40
valid_sources[0x77]	305958	1		T1	1242		T6	1858		T7	44
valid_sources[0x78]	307697	1		T1	1200		T6	1771		T7	39
valid_sources[0x79]	307849	1		T1	1115		T6	1812		T7	37
valid_sources[0x7a]	307056	1		T1	1197		T6	1844		T7	51
valid_sources[0x7b]	350833	1		T1	1100		T6	1881		T7	43
valid_sources[0x7c]	307670	1		T1	1151		T6	1861		T7	33
valid_sources[0x7d]	307965	1		T1	1144		T6	1895		T7	34
valid_sources[0x7e]	507956	1		T1	1222		T6	1885		T7	36
valid_sources[0x7f]	309168	1		T1	1097		T6	1817		T7	49
valid_sources[0x80]	311613	1		T1	1062		T6	1766		T7	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53474078

1

T1

147282

T3

3883

T4

30292

values[0x0]

all_enables

biggest_size

581611

1

T1

65

T3

13

T4

7

values[0x1]

all_enables

biggest_size

581486

1

T1

50

T3

8

T4

7