Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2021023	0	0
cfg0_rd_A	2147483647	6655	0	0
compare_lower0_0_rd_A	2147483647	6985	0	0
compare_upper0_0_rd_A	2147483647	6287	0	0
ctrl_rd_A	2147483647	6222	0	0
intr_enable0_rd_A	2147483647	8710	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2021023	0	0
T13	379067	91821	0	0
T14	0	65263	0	0
T15	0	116858	0	0
T28	0	341866	0	0
T29	0	338621	0	0
T30	0	332699	0	0
T31	0	103943	0	0
T32	0	86111	0	0
T33	0	88163	0	0
T34	0	83609	0	0
T35	142835	0	0	0
T36	171832	0	0	0
T37	133892	0	0	0
T38	197531	0	0	0
T39	334384	0	0	0
T40	300308	0	0	0
T41	102195	0	0	0
T42	670462	0	0	0
T43	368330	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6655	0	0
T13	379067	926	0	0
T15	0	616	0	0
T21	0	159	0	0
T23	0	181	0	0
T25	0	68	0	0
T27	0	10	0	0
T30	0	1640	0	0
T35	142835	0	0	0
T36	171832	0	0	0
T37	133892	0	0	0
T38	197531	0	0	0
T39	334384	0	0	0
T40	300308	0	0	0
T41	102195	0	0	0
T42	670462	0	0	0
T43	368330	0	0	0
T44	0	219	0	0
T45	0	13	0	0
T46	0	18	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6985	0	0
T13	379067	1230	0	0
T15	0	746	0	0
T21	0	121	0	0
T23	0	138	0	0
T25	0	81	0	0
T27	0	3	0	0
T30	0	1853	0	0
T35	142835	0	0	0
T36	171832	0	0	0
T37	133892	0	0	0
T38	197531	0	0	0
T39	334384	0	0	0
T40	300308	0	0	0
T41	102195	0	0	0
T42	670462	0	0	0
T43	368330	0	0	0
T44	0	256	0	0
T45	0	8	0	0
T46	0	27	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6287	0	0
T13	379067	955	0	0
T15	0	542	0	0
T21	0	115	0	0
T23	0	110	0	0
T25	0	85	0	0
T27	0	9	0	0
T30	0	1722	0	0
T35	142835	0	0	0
T36	171832	0	0	0
T37	133892	0	0	0
T38	197531	0	0	0
T39	334384	0	0	0
T40	300308	0	0	0
T41	102195	0	0	0
T42	670462	0	0	0
T43	368330	0	0	0
T44	0	231	0	0
T46	0	4	0	0
T47	0	453	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6222	0	0
T13	379067	948	0	0
T15	0	528	0	0
T21	0	112	0	0
T23	0	101	0	0
T25	0	87	0	0
T27	0	17	0	0
T30	0	1807	0	0
T35	142835	0	0	0
T36	171832	0	0	0
T37	133892	0	0	0
T38	197531	0	0	0
T39	334384	0	0	0
T40	300308	0	0	0
T41	102195	0	0	0
T42	670462	0	0	0
T43	368330	0	0	0
T44	0	203	0	0
T45	0	4	0	0
T46	0	15	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8710	0	0
T13	0	1333	0	0
T15	0	719	0	0
T16	8081	0	0	0
T30	0	2193	0	0
T48	686718	35	0	0
T49	0	132	0	0
T50	0	31	0	0
T51	0	33	0	0
T52	0	12	0	0
T53	0	38	0	0
T54	0	36	0	0
T55	164732	0	0	0
T56	104185	0	0	0
T57	204627	0	0	0
T58	113717	0	0	0
T59	828329	0	0	0
T60	123769	0	0	0
T61	469995	0	0	0
T62	37648	0	0	0