Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70972839	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	72045468	1		T1	300706		T2	701583		T3	938695

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142085864	1		T1	601664		T2	140296		T3	187537
values[0x0]	443577	1		T1	31		T2	29		T3	24
values[0x1]	488866	1		T1	18		T2	32		T3	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56696191	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	86322116	1		T1	360899		T2	842145		T3	112674

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1915271	1		T2	5491		T3	7217		T4	7024
valid_sources[0x01]	429868	1		T2	5430		T3	7294		T4	6879
valid_sources[0x02]	409435	1		T2	5553		T3	7292		T4	7053
valid_sources[0x03]	412879	1		T2	5446		T3	7311		T4	7101
valid_sources[0x04]	407565	1		T2	5551		T3	7414		T4	7032
valid_sources[0x05]	625814	1		T2	5419		T3	7326		T4	7132
valid_sources[0x06]	457955	1		T2	5453		T3	7283		T4	7065
valid_sources[0x07]	413911	1		T2	5417		T3	7517		T4	7111
valid_sources[0x08]	424943	1		T2	5470		T3	7330		T4	7073
valid_sources[0x09]	840831	1		T2	5540		T3	7132		T4	7084
valid_sources[0x0a]	409714	1		T2	5499		T3	7317		T4	7011
valid_sources[0x0b]	412437	1		T2	5425		T3	7362		T4	6968
valid_sources[0x0c]	411445	1		T2	5492		T3	7256		T4	6913
valid_sources[0x0d]	646404	1		T2	5443		T3	7349		T4	7109
valid_sources[0x0e]	410248	1		T2	5658		T3	7251		T4	7087
valid_sources[0x0f]	411007	1		T2	5693		T3	7407		T4	7034
valid_sources[0x10]	411780	1		T2	5548		T3	7251		T4	6963
valid_sources[0x11]	2604807	1		T2	5524		T3	7197		T4	6901
valid_sources[0x12]	411744	1		T2	5577		T3	7410		T4	6933
valid_sources[0x13]	707701	1		T2	5434		T3	7232		T4	6929
valid_sources[0x14]	413040	1		T2	5436		T3	7221		T4	6917
valid_sources[0x15]	502209	1		T2	5532		T3	7291		T4	7067
valid_sources[0x16]	413583	1		T2	5530		T3	7432		T4	6997
valid_sources[0x17]	408729	1		T2	5477		T3	7457		T4	7059
valid_sources[0x18]	412156	1		T2	5525		T3	7194		T4	6827
valid_sources[0x19]	412942	1		T2	5688		T3	7373		T4	6939
valid_sources[0x1a]	412143	1		T2	5360		T3	7439		T4	7114
valid_sources[0x1b]	413342	1		T2	5538		T3	7289		T4	6892
valid_sources[0x1c]	412815	1		T2	5483		T3	7176		T4	6902
valid_sources[0x1d]	1140003	1		T2	5540		T3	7326		T4	6935
valid_sources[0x1e]	409491	1		T2	5451		T3	7281		T4	6956
valid_sources[0x1f]	411858	1		T2	5462		T3	7315		T4	6988
valid_sources[0x20]	413713	1		T2	5350		T3	7359		T4	7021
valid_sources[0x21]	411091	1		T2	5331		T3	7430		T4	7227
valid_sources[0x22]	1594801	1		T2	5509		T3	7323		T4	7061
valid_sources[0x23]	411747	1		T2	5476		T3	7299		T4	7036
valid_sources[0x24]	412051	1		T2	5395		T3	7216		T4	7127
valid_sources[0x25]	496675	1		T2	5497		T3	7262		T4	6986
valid_sources[0x26]	413804	1		T2	5578		T3	7279		T4	6983
valid_sources[0x27]	410262	1		T2	5487		T3	7295		T4	6934
valid_sources[0x28]	410274	1		T2	5413		T3	7386		T4	7123
valid_sources[0x29]	410369	1		T2	5442		T3	7291		T4	6928
valid_sources[0x2a]	412033	1		T2	5519		T3	7245		T4	7129
valid_sources[0x2b]	412250	1		T2	5636		T3	7408		T4	7042
valid_sources[0x2c]	410196	1		T2	5542		T3	7415		T4	6998
valid_sources[0x2d]	844075	1		T2	5511		T3	7351		T4	7111
valid_sources[0x2e]	415155	1		T2	5526		T3	7320		T4	6924
valid_sources[0x2f]	415553	1		T2	5440		T3	7433		T4	7105
valid_sources[0x30]	494557	1		T2	5621		T3	7213		T4	7116
valid_sources[0x31]	411014	1		T2	5373		T3	7334		T4	7021
valid_sources[0x32]	408913	1		T2	5530		T3	7187		T4	7149
valid_sources[0x33]	1529860	1		T2	5481		T3	7274		T4	6983
valid_sources[0x34]	518126	1		T2	5486		T3	7199		T4	7187
valid_sources[0x35]	412591	1		T2	5496		T3	7472		T4	6984
valid_sources[0x36]	410459	1		T2	5526		T3	7311		T4	7154
valid_sources[0x37]	411770	1		T2	5491		T3	7387		T4	7144
valid_sources[0x38]	413914	1		T2	5548		T3	7434		T4	7259
valid_sources[0x39]	414667	1		T2	5396		T3	7478		T4	6981
valid_sources[0x3a]	410541	1		T2	5446		T3	7167		T4	6869
valid_sources[0x3b]	411783	1		T2	5326		T3	7353		T4	6937
valid_sources[0x3c]	432014	1		T2	5488		T3	7442		T4	7135
valid_sources[0x3d]	411724	1		T2	5430		T3	7368		T4	7077
valid_sources[0x3e]	412779	1		T2	5568		T3	7396		T4	7140
valid_sources[0x3f]	410585	1		T2	5567		T3	7323		T4	7023
valid_sources[0x40]	409315	1		T2	5517		T3	7339		T4	7047
valid_sources[0x41]	410941	1		T2	5372		T3	7049		T4	7097
valid_sources[0x42]	408120	1		T2	5483		T3	7236		T4	7007
valid_sources[0x43]	411111	1		T2	5426		T3	7321		T4	7054
valid_sources[0x44]	452820	1		T2	5456		T3	7319		T4	7211
valid_sources[0x45]	411653	1		T2	5553		T3	7343		T4	7120
valid_sources[0x46]	410423	1		T2	5410		T3	7235		T4	6980
valid_sources[0x47]	410033	1		T2	5483		T3	7461		T4	7091
valid_sources[0x48]	464723	1		T2	5477		T3	7069		T4	7048
valid_sources[0x49]	412979	1		T2	5411		T3	7262		T4	7159
valid_sources[0x4a]	412577	1		T2	5508		T3	7265		T4	7007
valid_sources[0x4b]	411000	1		T2	5499		T3	7454		T4	6976
valid_sources[0x4c]	411143	1		T2	5405		T3	7175		T4	7069
valid_sources[0x4d]	411107	1		T2	5376		T3	7267		T4	7066
valid_sources[0x4e]	408752	1		T2	5517		T3	7318		T4	6957
valid_sources[0x4f]	2471548	1		T2	5422		T3	7213		T4	6982
valid_sources[0x50]	471047	1		T2	5559		T3	7422		T4	7075
valid_sources[0x51]	415041	1		T2	5421		T3	7357		T4	6994
valid_sources[0x52]	412793	1		T2	5371		T3	7258		T4	7026
valid_sources[0x53]	412189	1		T2	5482		T3	7369		T4	7021
valid_sources[0x54]	413668	1		T2	5417		T3	7270		T4	6920
valid_sources[0x55]	410686	1		T2	5409		T3	7525		T4	6954
valid_sources[0x56]	1459246	1		T2	5418		T3	7384		T4	7005
valid_sources[0x57]	452138	1		T2	5417		T3	7267		T4	7127
valid_sources[0x58]	407563	1		T2	5541		T3	7273		T4	7113
valid_sources[0x59]	410309	1		T2	5433		T3	7409		T4	7099
valid_sources[0x5a]	457022	1		T2	5473		T3	7280		T4	6998
valid_sources[0x5b]	1183023	1		T2	5444		T3	7345		T4	6833
valid_sources[0x5c]	2682240	1		T2	5483		T3	7204		T4	7007
valid_sources[0x5d]	408011	1		T2	5504		T3	7355		T4	7072
valid_sources[0x5e]	409934	1		T2	5506		T3	7364		T4	6995
valid_sources[0x5f]	412677	1		T2	5378		T3	7409		T4	6989
valid_sources[0x60]	411776	1		T2	5435		T3	7433		T4	6947
valid_sources[0x61]	413752	1		T2	5437		T3	7166		T4	7126
valid_sources[0x62]	608247	1		T2	5383		T3	7461		T4	7069
valid_sources[0x63]	409038	1		T2	5421		T3	7439		T4	7007
valid_sources[0x64]	412794	1		T2	5488		T3	7313		T4	6916
valid_sources[0x65]	411582	1		T2	5452		T3	7251		T4	6938
valid_sources[0x66]	407942	1		T2	5632		T3	7343		T4	6980
valid_sources[0x67]	408299	1		T2	5634		T3	7027		T4	7111
valid_sources[0x68]	1011127	1		T1	601713		T2	5414		T3	7304
valid_sources[0x69]	412763	1		T2	5363		T3	7382		T4	7096
valid_sources[0x6a]	3628207	1		T2	5550		T3	7255		T4	6918
valid_sources[0x6b]	415780	1		T2	5394		T3	7086		T4	7034
valid_sources[0x6c]	409115	1		T2	5457		T3	7360		T4	7060
valid_sources[0x6d]	411864	1		T2	5379		T3	7367		T4	7131
valid_sources[0x6e]	410245	1		T2	5448		T3	7175		T4	6914
valid_sources[0x6f]	413611	1		T2	5401		T3	7345		T4	6877
valid_sources[0x70]	413398	1		T2	5392		T3	7479		T4	7113
valid_sources[0x71]	413334	1		T2	5388		T3	7494		T4	7354
valid_sources[0x72]	408851	1		T2	5490		T3	7381		T4	7127
valid_sources[0x73]	411515	1		T2	5410		T3	7290		T4	7062
valid_sources[0x74]	411613	1		T2	5564		T3	7373		T4	7062
valid_sources[0x75]	414955	1		T2	5649		T3	7310		T4	7073
valid_sources[0x76]	412248	1		T2	5402		T3	7371		T4	7167
valid_sources[0x77]	412667	1		T2	5517		T3	7354		T4	7150
valid_sources[0x78]	409790	1		T2	5303		T3	7383		T4	6977
valid_sources[0x79]	489462	1		T2	5471		T3	7235		T4	7022
valid_sources[0x7a]	412225	1		T2	5639		T3	7412		T4	7199
valid_sources[0x7b]	413752	1		T2	5548		T3	7341		T4	7065
valid_sources[0x7c]	667131	1		T2	5518		T3	7371		T4	7104
valid_sources[0x7d]	418036	1		T2	5506		T3	7431		T4	7067
valid_sources[0x7e]	413306	1		T2	5469		T3	7328		T4	7287
valid_sources[0x7f]	415528	1		T2	5447		T3	7554		T4	7034
valid_sources[0x80]	426895	1		T2	5493		T3	7157		T4	7046

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71179133

1

T1

300671

T2

701538

T3

938659

values[0x0]

all_enables

biggest_size

433992

1

T1

27

T2

23

T3

17

values[0x1]

all_enables

biggest_size

432343

1

T1

8

T2

22

T3

19