Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1489515	0	0
cfg0_rd_A	2147483647	4975	0	0
compare_lower0_0_rd_A	2147483647	4798	0	0
compare_upper0_0_rd_A	2147483647	4387	0	0
ctrl_rd_A	2147483647	4310	0	0
intr_enable0_rd_A	2147483647	5716	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1489515	0	0
T11	685808	27987	0	0
T12	4247	0	0	0
T14	0	236736	0	0
T15	0	314588	0	0
T36	0	76543	0	0
T37	0	75639	0	0
T38	0	117962	0	0
T39	0	21551	0	0
T40	0	60174	0	0
T41	0	172149	0	0
T42	0	219457	0	0
T43	12626	0	0	0
T44	481338	0	0	0
T45	406862	0	0	0
T46	446803	0	0	0
T47	143995	0	0	0
T48	714955	0	0	0
T49	229865	0	0	0
T50	159476	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4975	0	0
T30	0	109	0	0
T38	449207	1265	0	0
T39	515474	0	0	0
T41	0	1794	0	0
T51	0	642	0	0
T52	0	12	0	0
T53	0	39	0	0
T54	0	46	0	0
T55	0	30	0	0
T56	0	66	0	0
T57	0	2	0	0
T58	242548	0	0	0
T59	538935	0	0	0
T60	181642	0	0	0
T61	666510	0	0	0
T62	138236	0	0	0
T63	230853	0	0	0
T64	153444	0	0	0
T65	862790	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4798	0	0
T30	0	89	0	0
T38	449207	1432	0	0
T39	515474	0	0	0
T41	0	1893	0	0
T51	0	616	0	0
T52	0	6	0	0
T53	0	22	0	0
T54	0	39	0	0
T55	0	30	0	0
T56	0	9	0	0
T57	0	1	0	0
T58	242548	0	0	0
T59	538935	0	0	0
T60	181642	0	0	0
T61	666510	0	0	0
T62	138236	0	0	0
T63	230853	0	0	0
T64	153444	0	0	0
T65	862790	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4387	0	0
T30	0	96	0	0
T32	0	77	0	0
T38	449207	1190	0	0
T39	515474	0	0	0
T41	0	1679	0	0
T51	0	609	0	0
T53	0	14	0	0
T54	0	53	0	0
T55	0	24	0	0
T56	0	34	0	0
T57	0	5	0	0
T58	242548	0	0	0
T59	538935	0	0	0
T60	181642	0	0	0
T61	666510	0	0	0
T62	138236	0	0	0
T63	230853	0	0	0
T64	153444	0	0	0
T65	862790	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4310	0	0
T30	0	79	0	0
T32	0	47	0	0
T38	449207	1146	0	0
T39	515474	0	0	0
T41	0	1561	0	0
T51	0	653	0	0
T53	0	35	0	0
T54	0	60	0	0
T55	0	14	0	0
T56	0	44	0	0
T57	0	6	0	0
T58	242548	0	0	0
T59	538935	0	0	0
T60	181642	0	0	0
T61	666510	0	0	0
T62	138236	0	0	0
T63	230853	0	0	0
T64	153444	0	0	0
T65	862790	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5716	0	0
T38	0	1400	0	0
T41	0	1917	0	0
T51	0	766	0	0
T66	127835	44	0	0
T67	0	31	0	0
T68	0	24	0	0
T69	0	38	0	0
T70	0	7	0	0
T71	0	25	0	0
T72	0	156	0	0
T73	997518	0	0	0
T74	991660	0	0	0
T75	109159	0	0	0
T76	160651	0	0	0
T77	236632	0	0	0
T78	121773	0	0	0
T79	16795	0	0	0
T80	446129	0	0	0
T81	583630	0	0	0