Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54940654	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	55852128	1		T1	778		T2	77834		T3	43309

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	109998962	1		T1	1588		T2	155636		T3	86622
values[0x0]	377526	1		T1	2		T2	118		T3	44
values[0x1]	416294	1		T1	4		T2	75		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43884993	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	66907789	1		T1	955		T2	93576		T3	51941

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	291252	1		T2	577		T3	345		T5	423
valid_sources[0x01]	287642	1		T2	624		T3	334		T5	332
valid_sources[0x02]	320628	1		T2	612		T3	325		T5	358
valid_sources[0x03]	292632	1		T2	595		T3	306		T5	367
valid_sources[0x04]	289436	1		T2	646		T3	345		T5	349
valid_sources[0x05]	1032032	1		T2	584		T3	324		T5	355
valid_sources[0x06]	320434	1		T1	1		T2	589		T3	343
valid_sources[0x07]	291324	1		T2	569		T3	347		T5	375
valid_sources[0x08]	308590	1		T2	633		T3	314		T5	370
valid_sources[0x09]	292231	1		T2	583		T3	298		T5	352
valid_sources[0x0a]	368120	1		T2	590		T3	311		T5	329
valid_sources[0x0b]	453349	1		T1	67		T2	604		T3	347
valid_sources[0x0c]	293668	1		T2	651		T3	341		T5	326
valid_sources[0x0d]	290044	1		T2	609		T3	348		T5	313
valid_sources[0x0e]	2828382	1		T1	90		T2	636		T3	337
valid_sources[0x0f]	707222	1		T2	632		T3	323		T5	385
valid_sources[0x10]	290321	1		T2	610		T3	330		T5	413
valid_sources[0x11]	290114	1		T2	619		T3	320		T5	342
valid_sources[0x12]	293368	1		T2	655		T3	323		T5	348
valid_sources[0x13]	295460	1		T1	5		T2	625		T3	345
valid_sources[0x14]	290260	1		T2	587		T3	356		T5	338
valid_sources[0x15]	319739	1		T2	597		T3	361		T5	383
valid_sources[0x16]	291491	1		T2	637		T3	363		T5	374
valid_sources[0x17]	288658	1		T2	609		T3	342		T5	368
valid_sources[0x18]	290057	1		T2	639		T3	326		T5	398
valid_sources[0x19]	547238	1		T2	596		T3	357		T5	341
valid_sources[0x1a]	291346	1		T2	612		T3	347		T5	324
valid_sources[0x1b]	289749	1		T2	613		T3	330		T5	363
valid_sources[0x1c]	327672	1		T2	642		T3	344		T5	368
valid_sources[0x1d]	291217	1		T2	623		T3	297		T5	355
valid_sources[0x1e]	474143	1		T2	631		T3	340		T5	326
valid_sources[0x1f]	291587	1		T2	621		T3	338		T5	369
valid_sources[0x20]	289937	1		T1	24		T2	613		T3	366
valid_sources[0x21]	292580	1		T2	613		T3	355		T5	322
valid_sources[0x22]	292586	1		T1	19		T2	543		T3	367
valid_sources[0x23]	292145	1		T2	614		T3	378		T5	386
valid_sources[0x24]	522127	1		T2	583		T3	331		T5	341
valid_sources[0x25]	291321	1		T2	624		T3	288		T5	349
valid_sources[0x26]	290656	1		T2	629		T3	339		T5	337
valid_sources[0x27]	290872	1		T2	566		T3	356		T5	363
valid_sources[0x28]	291465	1		T2	631		T3	355		T5	395
valid_sources[0x29]	290524	1		T2	630		T3	328		T5	333
valid_sources[0x2a]	289359	1		T2	603		T3	350		T5	330
valid_sources[0x2b]	291698	1		T2	617		T3	338		T5	363
valid_sources[0x2c]	290431	1		T2	615		T3	327		T5	312
valid_sources[0x2d]	552432	1		T2	646		T3	344		T5	407
valid_sources[0x2e]	290434	1		T1	29		T2	568		T3	319
valid_sources[0x2f]	291069	1		T2	640		T3	352		T5	372
valid_sources[0x30]	291835	1		T2	597		T3	341		T5	351
valid_sources[0x31]	292281	1		T2	662		T3	361		T5	407
valid_sources[0x32]	292691	1		T2	616		T3	336		T5	356
valid_sources[0x33]	2386796	1		T2	600		T3	363		T5	339
valid_sources[0x34]	327405	1		T2	600		T3	312		T5	335
valid_sources[0x35]	294098	1		T1	12		T2	613		T3	357
valid_sources[0x36]	294218	1		T2	564		T3	342		T5	322
valid_sources[0x37]	291514	1		T2	555		T3	297		T5	309
valid_sources[0x38]	291733	1		T2	601		T3	344		T5	412
valid_sources[0x39]	296480	1		T2	608		T3	334		T5	373
valid_sources[0x3a]	290062	1		T2	576		T3	378		T5	356
valid_sources[0x3b]	294514	1		T2	621		T3	345		T5	394
valid_sources[0x3c]	293024	1		T2	600		T3	385		T5	342
valid_sources[0x3d]	351060	1		T2	610		T3	342		T5	341
valid_sources[0x3e]	356035	1		T2	589		T3	315		T5	384
valid_sources[0x3f]	290268	1		T1	137		T2	647		T3	334
valid_sources[0x40]	289820	1		T2	577		T3	346		T5	422
valid_sources[0x41]	1065943	1		T2	581		T3	348		T5	372
valid_sources[0x42]	486626	1		T1	209		T2	605		T3	347
valid_sources[0x43]	388516	1		T2	585		T3	355		T5	365
valid_sources[0x44]	292500	1		T2	584		T3	341		T5	347
valid_sources[0x45]	291239	1		T2	596		T3	346		T5	373
valid_sources[0x46]	659162	1		T2	595		T3	349		T5	315
valid_sources[0x47]	290970	1		T2	586		T3	359		T5	362
valid_sources[0x48]	294442	1		T2	605		T3	344		T5	316
valid_sources[0x49]	289039	1		T2	565		T3	326		T5	359
valid_sources[0x4a]	303852	1		T2	591		T3	353		T5	398
valid_sources[0x4b]	290947	1		T2	631		T3	336		T5	340
valid_sources[0x4c]	295654	1		T2	631		T3	334		T5	391
valid_sources[0x4d]	292833	1		T2	601		T3	361		T5	388
valid_sources[0x4e]	290127	1		T2	675		T3	299		T5	319
valid_sources[0x4f]	294638	1		T1	64		T2	565		T3	336
valid_sources[0x50]	289361	1		T2	559		T3	324		T5	338
valid_sources[0x51]	2625288	1		T2	620		T3	327		T5	360
valid_sources[0x52]	290549	1		T2	594		T3	324		T5	349
valid_sources[0x53]	292023	1		T2	610		T3	354		T5	386
valid_sources[0x54]	291902	1		T2	608		T3	334		T5	375
valid_sources[0x55]	290941	1		T2	609		T3	344		T5	341
valid_sources[0x56]	291322	1		T2	597		T3	380		T5	350
valid_sources[0x57]	289577	1		T2	616		T3	354		T5	324
valid_sources[0x58]	290428	1		T2	583		T3	353		T5	367
valid_sources[0x59]	292843	1		T2	598		T3	355		T5	323
valid_sources[0x5a]	291597	1		T2	571		T3	345		T5	315
valid_sources[0x5b]	291146	1		T2	592		T3	336		T5	362
valid_sources[0x5c]	296314	1		T1	7		T2	639		T3	352
valid_sources[0x5d]	301887	1		T2	640		T3	359		T5	334
valid_sources[0x5e]	292018	1		T2	568		T3	356		T5	387
valid_sources[0x5f]	291172	1		T1	43		T2	661		T3	344
valid_sources[0x60]	291662	1		T2	605		T3	357		T5	351
valid_sources[0x61]	288341	1		T2	609		T3	332		T5	344
valid_sources[0x62]	292040	1		T1	28		T2	608		T3	331
valid_sources[0x63]	295429	1		T2	643		T3	351		T5	372
valid_sources[0x64]	290942	1		T1	78		T2	618		T3	340
valid_sources[0x65]	292897	1		T2	584		T3	329		T5	422
valid_sources[0x66]	288799	1		T2	600		T3	300		T5	370
valid_sources[0x67]	290482	1		T2	587		T3	336		T5	366
valid_sources[0x68]	290828	1		T2	670		T3	323		T5	359
valid_sources[0x69]	306741	1		T2	600		T3	357		T5	410
valid_sources[0x6a]	379596	1		T1	142		T2	615		T3	332
valid_sources[0x6b]	293414	1		T2	632		T3	343		T5	414
valid_sources[0x6c]	290662	1		T2	620		T3	335		T5	358
valid_sources[0x6d]	292735	1		T2	548		T3	345		T5	420
valid_sources[0x6e]	493077	1		T1	2		T2	574		T3	318
valid_sources[0x6f]	292286	1		T2	590		T3	311		T5	381
valid_sources[0x70]	290160	1		T2	614		T3	306		T5	402
valid_sources[0x71]	539670	1		T2	631		T3	331		T5	369
valid_sources[0x72]	290727	1		T2	635		T3	334		T5	367
valid_sources[0x73]	288439	1		T2	609		T3	329		T5	370
valid_sources[0x74]	290777	1		T2	610		T3	345		T5	408
valid_sources[0x75]	618584	1		T2	607		T3	342		T5	355
valid_sources[0x76]	290070	1		T2	571		T3	317		T5	368
valid_sources[0x77]	291179	1		T2	605		T3	342		T5	374
valid_sources[0x78]	289104	1		T2	641		T3	340		T5	437
valid_sources[0x79]	289991	1		T2	632		T3	324		T5	391
valid_sources[0x7a]	462043	1		T2	607		T3	343		T5	416
valid_sources[0x7b]	748760	1		T2	589		T3	349		T5	366
valid_sources[0x7c]	1508637	1		T2	610		T3	335		T5	368
valid_sources[0x7d]	290676	1		T2	591		T3	351		T5	321
valid_sources[0x7e]	293099	1		T2	622		T3	343		T5	288
valid_sources[0x7f]	290510	1		T2	582		T3	329		T5	370
valid_sources[0x80]	287800	1		T2	631		T3	334		T5	383

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

55116245

1

T1

773

T2

77701

T3

43224

values[0x0]

all_enables

biggest_size

368845

1

T1

2

T2

86

T3

39

values[0x1]

all_enables

biggest_size

367038

1

T1

3

T2

47

T3

46