Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1270561	0	0
cfg0_rd_A	2147483647	4500	0	0
compare_lower0_0_rd_A	2147483647	4362	0	0
compare_upper0_0_rd_A	2147483647	3894	0	0
ctrl_rd_A	2147483647	4115	0	0
intr_enable0_rd_A	2147483647	5454	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1270561	0	0
T13	326672	89552	0	0
T14	0	89679	0	0
T15	0	111894	0	0
T36	0	240137	0	0
T37	0	150878	0	0
T38	0	156133	0	0
T39	0	71275	0	0
T40	0	261768	0	0
T41	0	87281	0	0
T42	0	258	0	0
T43	148034	0	0	0
T44	281218	0	0	0
T45	828901	0	0	0
T46	652685	0	0	0
T47	856179	0	0	0
T48	106662	0	0	0
T49	23765	0	0	0
T50	91505	0	0	0
T51	241111	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4500	0	0
T13	326672	502	0	0
T15	0	1088	0	0
T31	0	106	0	0
T33	0	30	0	0
T35	0	11	0	0
T37	0	1647	0	0
T42	0	1	0	0
T43	148034	0	0	0
T44	281218	0	0	0
T45	828901	0	0	0
T46	652685	0	0	0
T47	856179	0	0	0
T48	106662	0	0	0
T49	23765	0	0	0
T50	91505	0	0	0
T51	241111	0	0	0
T52	0	13	0	0
T53	0	22	0	0
T54	0	9	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4362	0	0
T13	326672	420	0	0
T15	0	1250	0	0
T31	0	51	0	0
T33	0	22	0	0
T35	0	24	0	0
T37	0	1682	0	0
T43	148034	0	0	0
T44	281218	0	0	0
T45	828901	0	0	0
T46	652685	0	0	0
T47	856179	0	0	0
T48	106662	0	0	0
T49	23765	0	0	0
T50	91505	0	0	0
T51	241111	0	0	0
T52	0	4	0	0
T53	0	20	0	0
T54	0	8	0	0
T55	0	1	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3894	0	0
T13	326672	358	0	0
T15	0	1015	0	0
T31	0	70	0	0
T33	0	13	0	0
T35	0	9	0	0
T37	0	1620	0	0
T43	148034	0	0	0
T44	281218	0	0	0
T45	828901	0	0	0
T46	652685	0	0	0
T47	856179	0	0	0
T48	106662	0	0	0
T49	23765	0	0	0
T50	91505	0	0	0
T51	241111	0	0	0
T52	0	4	0	0
T53	0	5	0	0
T54	0	1	0	0
T56	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4115	0	0
T13	326672	486	0	0
T15	0	1240	0	0
T31	0	57	0	0
T33	0	48	0	0
T35	0	14	0	0
T37	0	1364	0	0
T42	0	2	0	0
T43	148034	0	0	0
T44	281218	0	0	0
T45	828901	0	0	0
T46	652685	0	0	0
T47	856179	0	0	0
T48	106662	0	0	0
T49	23765	0	0	0
T50	91505	0	0	0
T51	241111	0	0	0
T52	0	12	0	0
T53	0	6	0	0
T54	0	2	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5454	0	0
T12	222990	68	0	0
T13	0	587	0	0
T15	0	1375	0	0
T37	0	1684	0	0
T57	0	139	0	0
T58	0	31	0	0
T59	0	12	0	0
T60	0	164	0	0
T61	0	68	0	0
T62	0	68	0	0
T63	158050	0	0	0
T64	125192	0	0	0
T65	637150	0	0	0
T66	468640	0	0	0
T67	3824	0	0	0
T68	170738	0	0	0
T69	647590	0	0	0
T70	490662	0	0	0
T71	142690	0	0	0