Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 56837028 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 57584091 1 T1 7265 T2 26 T3 404250



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 113778764 1 T1 14590 T2 32 T3 807536
values[0x0] 305710 1 T1 5 T2 3 T3 25
values[0x1] 336645 1 T1 14 T2 8 T3 25



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 45405969 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 69015150 1 T1 8741 T2 29 T3 485258



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 330844 1 T1 53 T3 3062 T4 304
valid_sources[0x01] 327249 1 T1 65 T3 3369 T4 285
valid_sources[0x02] 326194 1 T1 56 T3 2804 T4 328
valid_sources[0x03] 375227 1 T1 51 T3 3098 T4 326
valid_sources[0x04] 344204 1 T1 62 T3 3168 T4 326
valid_sources[0x05] 328857 1 T1 58 T3 3032 T4 330
valid_sources[0x06] 331165 1 T1 46 T3 2936 T4 324
valid_sources[0x07] 326632 1 T1 57 T3 3028 T4 291
valid_sources[0x08] 349244 1 T1 67 T3 3040 T4 306
valid_sources[0x09] 334931 1 T1 51 T3 3124 T4 318
valid_sources[0x0a] 822275 1 T1 47 T3 2911 T4 328
valid_sources[0x0b] 331384 1 T1 67 T3 3260 T4 317
valid_sources[0x0c] 326903 1 T1 61 T3 3107 T4 311
valid_sources[0x0d] 331620 1 T1 63 T3 3157 T4 299
valid_sources[0x0e] 558857 1 T1 65 T3 3171 T4 311
valid_sources[0x0f] 524291 1 T1 73 T3 3208 T4 340
valid_sources[0x10] 329393 1 T1 59 T3 3297 T4 291
valid_sources[0x11] 331352 1 T1 50 T2 2 T3 3067
valid_sources[0x12] 332901 1 T1 50 T3 3116 T4 315
valid_sources[0x13] 328843 1 T1 56 T3 3149 T4 343
valid_sources[0x14] 329800 1 T1 62 T3 2940 T4 306
valid_sources[0x15] 684988 1 T1 60 T3 3232 T4 314
valid_sources[0x16] 388276 1 T1 50 T3 2906 T4 302
valid_sources[0x17] 327284 1 T1 46 T3 3312 T4 311
valid_sources[0x18] 330042 1 T1 60 T2 1 T3 3140
valid_sources[0x19] 330931 1 T1 57 T3 3145 T4 346
valid_sources[0x1a] 328481 1 T1 64 T3 3138 T4 310
valid_sources[0x1b] 359504 1 T1 57 T3 3154 T4 313
valid_sources[0x1c] 329697 1 T1 53 T3 3226 T4 280
valid_sources[0x1d] 332551 1 T1 56 T3 3160 T4 307
valid_sources[0x1e] 329078 1 T1 68 T3 3243 T4 304
valid_sources[0x1f] 2302338 1 T1 59 T2 1 T3 3164
valid_sources[0x20] 332118 1 T1 46 T3 2939 T4 317
valid_sources[0x21] 329567 1 T1 48 T3 2892 T4 315
valid_sources[0x22] 340531 1 T1 54 T3 3218 T4 314
valid_sources[0x23] 329611 1 T1 54 T3 3130 T4 323
valid_sources[0x24] 331090 1 T1 51 T3 3247 T4 339
valid_sources[0x25] 327218 1 T1 54 T2 1 T3 3254
valid_sources[0x26] 330507 1 T1 60 T3 3308 T4 322
valid_sources[0x27] 322877 1 T1 59 T3 3068 T4 292
valid_sources[0x28] 326972 1 T1 52 T3 3176 T4 327
valid_sources[0x29] 328158 1 T1 68 T3 3242 T4 326
valid_sources[0x2a] 333774 1 T1 61 T3 3443 T4 297
valid_sources[0x2b] 330689 1 T1 40 T2 1 T3 3171
valid_sources[0x2c] 329943 1 T1 57 T3 3055 T4 302
valid_sources[0x2d] 552823 1 T1 66 T3 3090 T4 334
valid_sources[0x2e] 329412 1 T1 45 T3 2983 T4 280
valid_sources[0x2f] 328255 1 T1 56 T2 1 T3 3282
valid_sources[0x30] 452292 1 T1 58 T3 3532 T4 317
valid_sources[0x31] 332016 1 T1 69 T3 3371 T4 304
valid_sources[0x32] 329292 1 T1 64 T3 3113 T4 323
valid_sources[0x33] 329898 1 T1 58 T3 3091 T4 329
valid_sources[0x34] 551663 1 T1 51 T3 3119 T4 308
valid_sources[0x35] 329812 1 T1 55 T3 3051 T4 324
valid_sources[0x36] 328704 1 T1 49 T3 2957 T4 335
valid_sources[0x37] 326891 1 T1 57 T3 3172 T4 307
valid_sources[0x38] 1363598 1 T1 71 T3 3180 T4 332
valid_sources[0x39] 330904 1 T1 60 T3 3182 T4 323
valid_sources[0x3a] 330863 1 T1 71 T3 3056 T4 290
valid_sources[0x3b] 329535 1 T1 62 T3 3211 T4 310
valid_sources[0x3c] 328385 1 T1 55 T3 3248 T4 326
valid_sources[0x3d] 332168 1 T1 52 T3 3394 T4 299
valid_sources[0x3e] 2907078 1 T1 51 T3 3177 T4 319
valid_sources[0x3f] 329520 1 T1 59 T3 3131 T4 312
valid_sources[0x40] 330959 1 T1 58 T3 3061 T4 327
valid_sources[0x41] 704668 1 T1 65 T3 3168 T4 323
valid_sources[0x42] 331188 1 T1 63 T3 2981 T4 339
valid_sources[0x43] 329024 1 T1 55 T3 2971 T4 321
valid_sources[0x44] 448825 1 T1 60 T3 3011 T4 322
valid_sources[0x45] 331439 1 T1 52 T3 3387 T4 296
valid_sources[0x46] 1450829 1 T1 57 T3 3191 T4 302
valid_sources[0x47] 328635 1 T1 41 T2 4 T3 3035
valid_sources[0x48] 326179 1 T1 51 T3 2837 T4 310
valid_sources[0x49] 330103 1 T1 57 T3 3092 T4 285
valid_sources[0x4a] 328454 1 T1 72 T3 3231 T4 313
valid_sources[0x4b] 329432 1 T1 49 T2 1 T3 3158
valid_sources[0x4c] 358676 1 T1 55 T3 3131 T4 302
valid_sources[0x4d] 734393 1 T1 59 T3 3162 T4 300
valid_sources[0x4e] 329743 1 T1 43 T3 3100 T4 306
valid_sources[0x4f] 328220 1 T1 55 T3 3059 T4 326
valid_sources[0x50] 326787 1 T1 52 T2 1 T3 3052
valid_sources[0x51] 330243 1 T1 57 T3 3002 T4 314
valid_sources[0x52] 330971 1 T1 58 T3 3224 T4 303
valid_sources[0x53] 329153 1 T1 64 T2 1 T3 3222
valid_sources[0x54] 331143 1 T1 57 T3 3407 T4 314
valid_sources[0x55] 333113 1 T1 53 T3 3222 T4 313
valid_sources[0x56] 329466 1 T1 54 T3 3342 T4 318
valid_sources[0x57] 328395 1 T1 61 T3 2976 T4 318
valid_sources[0x58] 331045 1 T1 68 T3 3035 T4 303
valid_sources[0x59] 329682 1 T1 59 T3 3343 T4 319
valid_sources[0x5a] 333906 1 T1 56 T3 3136 T4 325
valid_sources[0x5b] 328952 1 T1 63 T3 3011 T4 341
valid_sources[0x5c] 329364 1 T1 59 T3 3030 T4 311
valid_sources[0x5d] 330766 1 T1 55 T3 3059 T4 315
valid_sources[0x5e] 367313 1 T1 48 T2 1 T3 3196
valid_sources[0x5f] 383722 1 T1 58 T3 2894 T4 306
valid_sources[0x60] 339326 1 T1 53 T3 2964 T4 297
valid_sources[0x61] 905769 1 T1 67 T3 3103 T4 302
valid_sources[0x62] 329987 1 T1 51 T3 3085 T4 328
valid_sources[0x63] 328283 1 T1 57 T3 3234 T4 323
valid_sources[0x64] 329465 1 T1 53 T3 3295 T4 319
valid_sources[0x65] 330142 1 T1 64 T3 3430 T4 299
valid_sources[0x66] 328379 1 T1 58 T3 3220 T4 313
valid_sources[0x67] 328716 1 T1 60 T3 3519 T4 313
valid_sources[0x68] 330579 1 T1 52 T3 3077 T4 304
valid_sources[0x69] 346991 1 T1 63 T3 3245 T4 326
valid_sources[0x6a] 329154 1 T1 52 T3 3148 T4 306
valid_sources[0x6b] 329642 1 T1 57 T3 2936 T4 289
valid_sources[0x6c] 412467 1 T1 57 T3 3249 T4 312
valid_sources[0x6d] 325626 1 T1 56 T2 1 T3 3058
valid_sources[0x6e] 351140 1 T1 55 T3 3306 T4 329
valid_sources[0x6f] 329601 1 T1 58 T3 3018 T4 310
valid_sources[0x70] 577157 1 T1 42 T3 3161 T4 331
valid_sources[0x71] 353772 1 T1 54 T3 3028 T4 351
valid_sources[0x72] 326889 1 T1 64 T3 3149 T4 275
valid_sources[0x73] 406214 1 T1 66 T2 1 T3 3169
valid_sources[0x74] 375650 1 T1 64 T3 3198 T4 307
valid_sources[0x75] 328205 1 T1 58 T3 3207 T4 322
valid_sources[0x76] 330239 1 T1 60 T3 3144 T4 311
valid_sources[0x77] 329462 1 T1 46 T2 2 T3 3016
valid_sources[0x78] 327783 1 T1 60 T3 3280 T4 301
valid_sources[0x79] 329241 1 T1 59 T3 3231 T4 342
valid_sources[0x7a] 330848 1 T1 55 T3 3380 T4 353
valid_sources[0x7b] 328557 1 T1 58 T3 3241 T4 325
valid_sources[0x7c] 599557 1 T1 45 T3 2955 T4 325
valid_sources[0x7d] 332982 1 T1 59 T3 3215 T4 304
valid_sources[0x7e] 329027 1 T1 59 T3 3275 T4 324
valid_sources[0x7f] 329395 1 T1 47 T3 2957 T4 318
valid_sources[0x80] 343260 1 T1 48 T3 3175 T4 311



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 56989702 1 T1 7251 T2 18 T3 404214
values[0x0] all_enables biggest_size 298036 1 T1 4 T2 3 T3 19
values[0x1] all_enables biggest_size 296353 1 T1 10 T2 5 T3 17

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%