Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1006862	0	0
cfg0_rd_A	2147483647	6770	0	0
compare_lower0_0_rd_A	2147483647	6918	0	0
compare_upper0_0_rd_A	2147483647	6094	0	0
ctrl_rd_A	2147483647	6303	0	0
intr_enable0_rd_A	2147483647	7465	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1006862	0	0
T13	181585	75457	0	0
T14	0	139919	0	0
T15	0	32864	0	0
T30	0	8	0	0
T34	0	37	0	0
T37	0	160941	0	0
T38	0	164905	0	0
T39	0	285823	0	0
T40	0	44186	0	0
T41	0	90296	0	0
T42	607920	0	0	0
T43	158863	0	0	0
T44	370550	0	0	0
T45	362696	0	0	0
T46	110117	0	0	0
T47	170897	0	0	0
T48	128356	0	0	0
T49	484170	0	0	0
T50	453533	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6770	0	0
T14	548884	1149	0	0
T15	131303	417	0	0
T30	0	137	0	0
T34	0	5	0	0
T38	0	1655	0	0
T51	0	10	0	0
T52	0	130	0	0
T53	0	65	0	0
T54	0	23	0	0
T55	0	424	0	0
T56	591371	0	0	0
T57	328659	0	0	0
T58	136928	0	0	0
T59	134269	0	0	0
T60	185580	0	0	0
T61	358236	0	0	0
T62	184588	0	0	0
T63	1448	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6918	0	0
T14	548884	1630	0	0
T15	131303	369	0	0
T30	0	92	0	0
T34	0	7	0	0
T38	0	1910	0	0
T51	0	6	0	0
T52	0	105	0	0
T53	0	46	0	0
T54	0	11	0	0
T55	0	474	0	0
T56	591371	0	0	0
T57	328659	0	0	0
T58	136928	0	0	0
T59	134269	0	0	0
T60	185580	0	0	0
T61	358236	0	0	0
T62	184588	0	0	0
T63	1448	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6094	0	0
T14	548884	1347	0	0
T15	131303	336	0	0
T30	0	66	0	0
T34	0	5	0	0
T38	0	1534	0	0
T51	0	10	0	0
T52	0	78	0	0
T53	0	61	0	0
T54	0	12	0	0
T55	0	447	0	0
T56	591371	0	0	0
T57	328659	0	0	0
T58	136928	0	0	0
T59	134269	0	0	0
T60	185580	0	0	0
T61	358236	0	0	0
T62	184588	0	0	0
T63	1448	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6303	0	0
T14	548884	1398	0	0
T15	131303	334	0	0
T30	0	72	0	0
T34	0	12	0	0
T38	0	1682	0	0
T51	0	13	0	0
T52	0	78	0	0
T53	0	95	0	0
T54	0	27	0	0
T55	0	377	0	0
T56	591371	0	0	0
T57	328659	0	0	0
T58	136928	0	0	0
T59	134269	0	0	0
T60	185580	0	0	0
T61	358236	0	0	0
T62	184588	0	0	0
T63	1448	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7465	0	0
T14	0	1559	0	0
T15	0	457	0	0
T36	112526	5	0	0
T38	0	1961	0	0
T64	0	52	0	0
T65	0	29	0	0
T66	0	29	0	0
T67	0	84	0	0
T68	0	58	0	0
T69	0	68	0	0
T70	106516	0	0	0
T71	290122	0	0	0
T72	659869	0	0	0
T73	326926	0	0	0
T74	856757	0	0	0
T75	614673	0	0	0
T76	840846	0	0	0
T77	311486	0	0	0
T78	580808	0	0	0