Unified Coverage Report :: Module :: timer_core

Module : timer_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_harts[0].u_core	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_harts[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : timer_core

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	28	7	7	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
30	1	1
31	1	1
32	1	1
33	1	1
35	1	1
39	1	1
41	1	1
45	1	1

---

Cond Coverage for Module : timer_core

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       32
 EXPRESSION (tick_count == prescaler)
            ------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T3,T5,T6

 LINE       39
 EXPRESSION (active & (tick_count >= prescaler))
             ---1--   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T3,T5,T6

 LINE       45
 EXPRESSION (active & (mtime >= mtimecmp[0]))
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T3,T5
1	1	Covered	T3,T5,T6

---

Branch Coverage for Module : timer_core

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv' or '../src/lowrisc_ip_rv_timer_0.1/rtl/timer_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_ni))
-2-:	30	if ((!active))
-3-:	32	if ((tick_count == prescaler))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T2,T3,T5