Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1694419	0	0
cfg0_rd_A	2147483647	3438	0	0
compare_lower0_0_rd_A	2147483647	3577	0	0
compare_upper0_0_rd_A	2147483647	3409	0	0
ctrl_rd_A	2147483647	3198	0	0
intr_enable0_rd_A	2147483647	4792	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1694419	0	0
T11	109365	31681	0	0
T12	0	56038	0	0
T13	0	282828	0	0
T36	0	57422	0	0
T37	0	325443	0	0
T38	0	257099	0	0
T39	0	424928	0	0
T40	0	31853	0	0
T41	0	212782	0	0
T42	0	689	0	0
T43	905927	0	0	0
T44	196007	0	0	0
T45	157118	0	0	0
T46	421537	0	0	0
T47	187561	0	0	0
T48	239588	0	0	0
T49	557371	0	0	0
T50	178974	0	0	0
T51	142731	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3438	0	0
T12	231206	588	0	0
T13	124038	1526	0	0
T28	0	102	0	0
T40	0	251	0	0
T52	0	172	0	0
T53	0	4	0	0
T54	0	4	0	0
T55	0	22	0	0
T56	0	52	0	0
T57	0	2	0	0
T58	164379	0	0	0
T59	162977	0	0	0
T60	521383	0	0	0
T61	113699	0	0	0
T62	645251	0	0	0
T63	953030	0	0	0
T64	666617	0	0	0
T65	383458	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3577	0	0
T12	231206	654	0	0
T13	124038	1829	0	0
T28	0	53	0	0
T40	0	330	0	0
T52	0	121	0	0
T55	0	13	0	0
T56	0	21	0	0
T57	0	1	0	0
T58	164379	0	0	0
T59	162977	0	0	0
T60	521383	0	0	0
T61	113699	0	0	0
T62	645251	0	0	0
T63	953030	0	0	0
T64	666617	0	0	0
T65	383458	0	0	0
T66	0	12	0	0
T67	0	37	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3409	0	0
T12	231206	643	0	0
T13	124038	1523	0	0
T28	0	80	0	0
T40	0	297	0	0
T52	0	169	0	0
T54	0	4	0	0
T55	0	15	0	0
T56	0	16	0	0
T57	0	6	0	0
T58	164379	0	0	0
T59	162977	0	0	0
T60	521383	0	0	0
T61	113699	0	0	0
T62	645251	0	0	0
T63	953030	0	0	0
T64	666617	0	0	0
T65	383458	0	0	0
T66	0	8	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3198	0	0
T12	231206	515	0	0
T13	124038	1557	0	0
T28	0	79	0	0
T40	0	270	0	0
T52	0	104	0	0
T55	0	18	0	0
T56	0	31	0	0
T57	0	7	0	0
T58	164379	0	0	0
T59	162977	0	0	0
T60	521383	0	0	0
T61	113699	0	0	0
T62	645251	0	0	0
T63	953030	0	0	0
T64	666617	0	0	0
T65	383458	0	0	0
T66	0	10	0	0
T67	0	24	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4792	0	0
T12	0	720	0	0
T13	0	1843	0	0
T68	157850	37	0	0
T69	0	45	0	0
T70	0	51	0	0
T71	0	120	0	0
T72	0	57	0	0
T73	0	34	0	0
T74	0	40	0	0
T75	0	17	0	0
T76	111977	0	0	0
T77	261678	0	0	0
T78	717047	0	0	0
T79	944786	0	0	0
T80	692668	0	0	0
T81	915866	0	0	0
T82	125235	0	0	0
T83	808396	0	0	0
T84	295641	0	0	0