Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57170549	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	58515469	1		T1	55152		T2	9066		T3	52867

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	114524845	1		T1	110147		T2	18052		T3	105405
values[0x0]	552043	1		T1	30		T2	11		T3	22
values[0x1]	609130	1		T1	40		T2	10		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45653120	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	70032898	1		T1	66248		T2	10909		T3	63448

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	331461	1		T1	442		T2	67		T3	322
valid_sources[0x01]	322211	1		T1	448		T2	83		T3	349
valid_sources[0x02]	425732	1		T1	391		T2	85		T3	374
valid_sources[0x03]	319859	1		T1	424		T2	77		T3	370
valid_sources[0x04]	322216	1		T1	395		T2	73		T3	383
valid_sources[0x05]	325677	1		T1	428		T2	69		T3	503
valid_sources[0x06]	338288	1		T1	420		T2	56		T3	458
valid_sources[0x07]	326877	1		T1	430		T2	75		T3	398
valid_sources[0x08]	319980	1		T1	404		T2	74		T3	406
valid_sources[0x09]	500012	1		T1	450		T2	64		T3	416
valid_sources[0x0a]	323263	1		T1	447		T2	69		T3	451
valid_sources[0x0b]	3789967	1		T1	499		T2	62		T3	435
valid_sources[0x0c]	320034	1		T1	434		T2	68		T3	390
valid_sources[0x0d]	347910	1		T1	470		T2	90		T3	387
valid_sources[0x0e]	332207	1		T1	501		T2	74		T3	339
valid_sources[0x0f]	330362	1		T1	470		T2	62		T3	383
valid_sources[0x10]	324836	1		T1	452		T2	87		T3	373
valid_sources[0x11]	600021	1		T1	518		T2	65		T3	558
valid_sources[0x12]	353066	1		T1	458		T2	65		T3	443
valid_sources[0x13]	325249	1		T1	356		T2	67		T3	344
valid_sources[0x14]	707474	1		T1	446		T2	64		T3	407
valid_sources[0x15]	326619	1		T1	436		T2	64		T3	430
valid_sources[0x16]	801093	1		T1	463		T2	78		T3	358
valid_sources[0x17]	371058	1		T1	407		T2	76		T3	350
valid_sources[0x18]	320386	1		T1	467		T2	67		T3	507
valid_sources[0x19]	326410	1		T1	426		T2	69		T3	492
valid_sources[0x1a]	320462	1		T1	473		T2	71		T3	468
valid_sources[0x1b]	434429	1		T1	453		T2	66		T3	427
valid_sources[0x1c]	463749	1		T1	426		T2	70		T3	393
valid_sources[0x1d]	321420	1		T1	403		T2	78		T3	457
valid_sources[0x1e]	320640	1		T1	509		T2	66		T3	385
valid_sources[0x1f]	322529	1		T1	398		T2	72		T3	403
valid_sources[0x20]	321894	1		T1	403		T2	66		T3	326
valid_sources[0x21]	327362	1		T1	382		T2	86		T3	389
valid_sources[0x22]	1960319	1		T1	411		T2	67		T3	378
valid_sources[0x23]	324974	1		T1	444		T2	84		T3	383
valid_sources[0x24]	322929	1		T1	443		T2	58		T3	416
valid_sources[0x25]	321275	1		T1	380		T2	86		T3	434
valid_sources[0x26]	326702	1		T1	351		T2	67		T3	477
valid_sources[0x27]	323871	1		T1	411		T2	65		T3	420
valid_sources[0x28]	450273	1		T1	444		T2	67		T3	369
valid_sources[0x29]	321593	1		T1	429		T2	56		T3	443
valid_sources[0x2a]	323305	1		T1	401		T2	82		T3	350
valid_sources[0x2b]	326389	1		T1	421		T2	68		T3	334
valid_sources[0x2c]	320467	1		T1	411		T2	68		T3	391
valid_sources[0x2d]	1404823	1		T1	430		T2	51		T3	438
valid_sources[0x2e]	324975	1		T1	479		T2	71		T3	493
valid_sources[0x2f]	322236	1		T1	460		T2	65		T3	408
valid_sources[0x30]	323907	1		T1	409		T2	71		T3	335
valid_sources[0x31]	881607	1		T1	526		T2	75		T3	458
valid_sources[0x32]	436220	1		T1	418		T2	73		T3	505
valid_sources[0x33]	325078	1		T1	436		T2	66		T3	476
valid_sources[0x34]	323353	1		T1	420		T2	60		T3	384
valid_sources[0x35]	319497	1		T1	420		T2	85		T3	451
valid_sources[0x36]	321348	1		T1	428		T2	81		T3	403
valid_sources[0x37]	324063	1		T1	468		T2	81		T3	321
valid_sources[0x38]	324585	1		T1	417		T2	71		T3	489
valid_sources[0x39]	322370	1		T1	452		T2	61		T3	325
valid_sources[0x3a]	409186	1		T1	470		T2	59		T3	360
valid_sources[0x3b]	320151	1		T1	477		T2	75		T3	356
valid_sources[0x3c]	322622	1		T1	441		T2	86		T3	440
valid_sources[0x3d]	634866	1		T1	462		T2	69		T3	499
valid_sources[0x3e]	858820	1		T1	431		T2	74		T3	506
valid_sources[0x3f]	322670	1		T1	454		T2	72		T3	430
valid_sources[0x40]	324793	1		T1	466		T2	66		T3	347
valid_sources[0x41]	638486	1		T1	458		T2	65		T3	459
valid_sources[0x42]	322555	1		T1	492		T2	85		T3	462
valid_sources[0x43]	321080	1		T1	418		T2	76		T3	412
valid_sources[0x44]	325338	1		T1	446		T2	61		T3	406
valid_sources[0x45]	384822	1		T1	404		T2	67		T3	492
valid_sources[0x46]	323046	1		T1	436		T2	67		T3	493
valid_sources[0x47]	320898	1		T1	418		T2	81		T3	410
valid_sources[0x48]	327619	1		T1	360		T2	72		T3	354
valid_sources[0x49]	1152839	1		T1	480		T2	70		T3	366
valid_sources[0x4a]	327333	1		T1	473		T2	72		T3	538
valid_sources[0x4b]	324012	1		T1	443		T2	66		T3	467
valid_sources[0x4c]	730419	1		T1	500		T2	71		T3	533
valid_sources[0x4d]	2551226	1		T1	443		T2	71		T3	401
valid_sources[0x4e]	320959	1		T1	454		T2	64		T3	405
valid_sources[0x4f]	324470	1		T1	395		T2	68		T3	526
valid_sources[0x50]	322637	1		T1	452		T2	78		T3	395
valid_sources[0x51]	320304	1		T1	467		T2	70		T3	404
valid_sources[0x52]	493228	1		T1	388		T2	58		T3	436
valid_sources[0x53]	323563	1		T1	385		T2	71		T3	394
valid_sources[0x54]	908812	1		T1	411		T2	73		T3	449
valid_sources[0x55]	325060	1		T1	436		T2	72		T3	390
valid_sources[0x56]	324735	1		T1	479		T2	82		T3	471
valid_sources[0x57]	323723	1		T1	474		T2	69		T3	462
valid_sources[0x58]	332672	1		T1	352		T2	73		T3	379
valid_sources[0x59]	324951	1		T1	424		T2	95		T3	352
valid_sources[0x5a]	1193490	1		T1	409		T2	77		T3	351
valid_sources[0x5b]	319256	1		T1	428		T2	57		T3	472
valid_sources[0x5c]	382364	1		T1	418		T2	73		T3	364
valid_sources[0x5d]	330494	1		T1	421		T2	78		T3	402
valid_sources[0x5e]	321942	1		T1	462		T2	76		T3	476
valid_sources[0x5f]	321928	1		T1	427		T2	69		T3	411
valid_sources[0x60]	322719	1		T1	406		T2	78		T3	452
valid_sources[0x61]	318895	1		T1	470		T2	70		T3	342
valid_sources[0x62]	324115	1		T1	408		T2	93		T3	375
valid_sources[0x63]	325326	1		T1	448		T2	80		T3	423
valid_sources[0x64]	325342	1		T1	429		T2	76		T3	270
valid_sources[0x65]	326000	1		T1	411		T2	71		T3	385
valid_sources[0x66]	321336	1		T1	409		T2	80		T3	477
valid_sources[0x67]	330513	1		T1	453		T2	67		T3	423
valid_sources[0x68]	319186	1		T1	407		T2	79		T3	387
valid_sources[0x69]	328366	1		T1	485		T2	57		T3	452
valid_sources[0x6a]	327836	1		T1	435		T2	71		T3	403
valid_sources[0x6b]	397551	1		T1	470		T2	66		T3	522
valid_sources[0x6c]	321828	1		T1	485		T2	53		T3	426
valid_sources[0x6d]	319469	1		T1	421		T2	78		T3	464
valid_sources[0x6e]	325838	1		T1	408		T2	70		T3	480
valid_sources[0x6f]	320545	1		T1	416		T2	69		T3	400
valid_sources[0x70]	323077	1		T1	442		T2	73		T3	504
valid_sources[0x71]	318422	1		T1	409		T2	76		T3	358
valid_sources[0x72]	565992	1		T1	363		T2	58		T3	461
valid_sources[0x73]	323789	1		T1	459		T2	73		T3	488
valid_sources[0x74]	324161	1		T1	404		T2	77		T3	344
valid_sources[0x75]	329704	1		T1	433		T2	86		T3	275
valid_sources[0x76]	1773576	1		T1	401		T2	65		T3	434
valid_sources[0x77]	370098	1		T1	406		T2	69		T3	354
valid_sources[0x78]	1572939	1		T1	401		T2	67		T3	486
valid_sources[0x79]	325988	1		T1	414		T2	71		T3	405
valid_sources[0x7a]	327695	1		T1	457		T2	52		T3	431
valid_sources[0x7b]	1454671	1		T1	397		T2	48		T3	393
valid_sources[0x7c]	574770	1		T1	415		T2	59		T3	453
valid_sources[0x7d]	325454	1		T1	469		T2	72		T3	417
valid_sources[0x7e]	321684	1		T1	386		T2	63		T3	457
valid_sources[0x7f]	353584	1		T1	427		T2	69		T3	373
valid_sources[0x80]	383524	1		T1	398		T2	71		T3	341

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

57435562

1

T1

55092

T2

9050

T3

52829

values[0x0]

all_enables

biggest_size

541080

1

T1

29

T2

9

T3

15

values[0x1]

all_enables

biggest_size

538827

1

T1

31

T2

7

T3

23