Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1883265	0	0
cfg0_rd_A	2147483647	4376	0	0
compare_lower0_0_rd_A	2147483647	4655	0	0
compare_upper0_0_rd_A	2147483647	4317	0	0
ctrl_rd_A	2147483647	3974	0	0
intr_enable0_rd_A	2147483647	5670	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1883265	0	0
T14	113964	29333	0	0
T15	0	236455	0	0
T16	0	87435	0	0
T36	0	170892	0	0
T37	0	190627	0	0
T38	0	129206	0	0
T39	0	224408	0	0
T40	0	59367	0	0
T41	0	192834	0	0
T42	0	247294	0	0
T43	105441	0	0	0
T44	357616	0	0	0
T45	158620	0	0	0
T46	596841	0	0	0
T47	555033	0	0	0
T48	123996	0	0	0
T49	303791	0	0	0
T50	804125	0	0	0
T51	192860	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4376	0	0
T14	113964	289	0	0
T32	0	96	0	0
T35	0	8	0	0
T39	0	1368	0	0
T40	0	569	0	0
T43	105441	0	0	0
T44	357616	0	0	0
T45	158620	0	0	0
T46	596841	0	0	0
T47	555033	0	0	0
T48	123996	0	0	0
T49	303791	0	0	0
T50	804125	0	0	0
T51	192860	0	0	0
T52	0	7	0	0
T53	0	31	0	0
T54	0	46	0	0
T55	0	207	0	0
T56	0	212	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4655	0	0
T14	113964	456	0	0
T32	0	101	0	0
T35	0	8	0	0
T39	0	1368	0	0
T40	0	737	0	0
T43	105441	0	0	0
T44	357616	0	0	0
T45	158620	0	0	0
T46	596841	0	0	0
T47	555033	0	0	0
T48	123996	0	0	0
T49	303791	0	0	0
T50	804125	0	0	0
T51	192860	0	0	0
T53	0	12	0	0
T54	0	93	0	0
T55	0	246	0	0
T56	0	116	0	0
T57	0	47	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4317	0	0
T14	113964	391	0	0
T32	0	56	0	0
T35	0	3	0	0
T39	0	1250	0	0
T40	0	703	0	0
T43	105441	0	0	0
T44	357616	0	0	0
T45	158620	0	0	0
T46	596841	0	0	0
T47	555033	0	0	0
T48	123996	0	0	0
T49	303791	0	0	0
T50	804125	0	0	0
T51	192860	0	0	0
T52	0	7	0	0
T53	0	17	0	0
T54	0	97	0	0
T55	0	243	0	0
T56	0	102	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3974	0	0
T14	113964	290	0	0
T32	0	80	0	0
T35	0	1	0	0
T39	0	1207	0	0
T40	0	548	0	0
T43	105441	0	0	0
T44	357616	0	0	0
T45	158620	0	0	0
T46	596841	0	0	0
T47	555033	0	0	0
T48	123996	0	0	0
T49	303791	0	0	0
T50	804125	0	0	0
T51	192860	0	0	0
T52	0	15	0	0
T53	0	12	0	0
T54	0	25	0	0
T55	0	205	0	0
T56	0	107	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5670	0	0
T9	438902	72	0	0
T10	689834	17	0	0
T11	164073	0	0	0
T12	132628	0	0	0
T13	650395	0	0	0
T14	0	442	0	0
T58	325031	30	0	0
T59	0	25	0	0
T60	0	43	0	0
T61	0	30	0	0
T62	0	81	0	0
T63	0	20	0	0
T64	0	99	0	0
T65	307645	0	0	0
T66	69696	0	0	0
T67	714593	0	0	0
T68	301034	0	0	0