Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2218078	0	0
cfg0_rd_A	2147483647	8530	0	0
compare_lower0_0_rd_A	2147483647	9028	0	0
compare_upper0_0_rd_A	2147483647	7894	0	0
ctrl_rd_A	2147483647	7902	0	0
intr_enable0_rd_A	2147483647	10230	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2218078	0	0
T5	617507	165051	0	0
T6	869848	0	0	0
T7	137221	0	0	0
T8	113016	0	0	0
T9	141020	0	0	0
T10	446975	0	0	0
T11	0	42738	0	0
T12	0	149160	0	0
T33	0	273028	0	0
T34	0	44620	0	0
T35	0	263396	0	0
T36	0	132479	0	0
T37	0	167489	0	0
T38	0	338752	0	0
T39	0	156354	0	0
T40	495598	0	0	0
T41	146111	0	0	0
T42	413563	0	0	0
T43	940840	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8530	0	0
T30	0	74	0	0
T34	174934	513	0	0
T35	0	2579	0	0
T44	0	823	0	0
T45	0	3014	0	0
T46	0	18	0	0
T47	0	7	0	0
T48	0	2	0	0
T49	0	14	0	0
T50	0	8	0	0
T51	138108	0	0	0
T52	155170	0	0	0
T53	123966	0	0	0
T54	585554	0	0	0
T55	996489	0	0	0
T56	136880	0	0	0
T57	328408	0	0	0
T58	229403	0	0	0
T59	636748	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9028	0	0
T30	0	31	0	0
T34	174934	443	0	0
T35	0	3003	0	0
T44	0	1014	0	0
T45	0	3210	0	0
T46	0	6	0	0
T48	0	4	0	0
T49	0	14	0	0
T50	0	11	0	0
T51	138108	0	0	0
T52	155170	0	0	0
T53	123966	0	0	0
T54	585554	0	0	0
T55	996489	0	0	0
T56	136880	0	0	0
T57	328408	0	0	0
T58	229403	0	0	0
T59	636748	0	0	0
T60	0	1	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7894	0	0
T30	0	34	0	0
T34	174934	420	0	0
T35	0	2439	0	0
T44	0	728	0	0
T45	0	2906	0	0
T46	0	19	0	0
T48	0	5	0	0
T49	0	3	0	0
T51	138108	0	0	0
T52	155170	0	0	0
T53	123966	0	0	0
T54	585554	0	0	0
T55	996489	0	0	0
T56	136880	0	0	0
T57	328408	0	0	0
T58	229403	0	0	0
T59	636748	0	0	0
T61	0	1	0	0
T62	0	13	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7902	0	0
T30	0	45	0	0
T34	174934	479	0	0
T35	0	2583	0	0
T44	0	668	0	0
T45	0	2814	0	0
T46	0	1	0	0
T48	0	4	0	0
T49	0	3	0	0
T50	0	2	0	0
T51	138108	0	0	0
T52	155170	0	0	0
T53	123966	0	0	0
T54	585554	0	0	0
T55	996489	0	0	0
T56	136880	0	0	0
T57	328408	0	0	0
T58	229403	0	0	0
T59	636748	0	0	0
T60	0	4	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10230	0	0
T34	174934	524	0	0
T35	0	2877	0	0
T51	138108	0	0	0
T52	155170	0	0	0
T53	123966	0	0	0
T54	585554	0	0	0
T55	996489	11	0	0
T56	136880	0	0	0
T57	328408	0	0	0
T58	229403	0	0	0
T59	636748	0	0	0
T63	0	48	0	0
T64	0	6	0	0
T65	0	20	0	0
T66	0	30	0	0
T67	0	23	0	0
T68	0	12	0	0
T69	0	115	0	0