Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1353532	0	0
cfg0_rd_A	2147483647	9311	0	0
compare_lower0_0_rd_A	2147483647	10142	0	0
compare_upper0_0_rd_A	2147483647	9068	0	0
ctrl_rd_A	2147483647	9164	0	0
intr_enable0_rd_A	2147483647	11931	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1353532	0	0
T11	525748	121877	0	0
T12	0	123904	0	0
T13	0	94271	0	0
T33	0	155011	0	0
T34	0	92850	0	0
T35	0	287125	0	0
T36	0	81495	0	0
T37	0	61021	0	0
T38	0	164583	0	0
T39	0	158295	0	0
T40	216162	0	0	0
T41	902871	0	0	0
T42	585414	0	0	0
T43	134922	0	0	0
T44	112216	0	0	0
T45	158941	0	0	0
T46	376435	0	0	0
T47	120130	0	0	0
T48	706200	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9311	0	0
T11	525748	1169	0	0
T13	0	896	0	0
T29	0	59	0	0
T35	0	1659	0	0
T36	0	799	0	0
T38	0	830	0	0
T39	0	1525	0	0
T40	216162	0	0	0
T41	902871	0	0	0
T42	585414	0	0	0
T43	134922	0	0	0
T44	112216	0	0	0
T45	158941	0	0	0
T46	376435	0	0	0
T47	120130	0	0	0
T48	706200	0	0	0
T49	0	8	0	0
T50	0	3	0	0
T51	0	35	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10142	0	0
T11	525748	1421	0	0
T13	0	1110	0	0
T29	0	35	0	0
T35	0	1622	0	0
T36	0	983	0	0
T38	0	1046	0	0
T39	0	1887	0	0
T40	216162	0	0	0
T41	902871	0	0	0
T42	585414	0	0	0
T43	134922	0	0	0
T44	112216	0	0	0
T45	158941	0	0	0
T46	376435	0	0	0
T47	120130	0	0	0
T48	706200	0	0	0
T49	0	4	0	0
T51	0	26	0	0
T52	0	74	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9068	0	0
T11	525748	1330	0	0
T13	0	1011	0	0
T29	0	45	0	0
T35	0	1590	0	0
T36	0	818	0	0
T38	0	855	0	0
T39	0	1439	0	0
T40	216162	0	0	0
T41	902871	0	0	0
T42	585414	0	0	0
T43	134922	0	0	0
T44	112216	0	0	0
T45	158941	0	0	0
T46	376435	0	0	0
T47	120130	0	0	0
T48	706200	0	0	0
T49	0	10	0	0
T50	0	18	0	0
T51	0	68	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9164	0	0
T11	525748	1368	0	0
T13	0	963	0	0
T29	0	32	0	0
T35	0	1465	0	0
T36	0	820	0	0
T38	0	1027	0	0
T39	0	1481	0	0
T40	216162	0	0	0
T41	902871	0	0	0
T42	585414	0	0	0
T43	134922	0	0	0
T44	112216	0	0	0
T45	158941	0	0	0
T46	376435	0	0	0
T47	120130	0	0	0
T48	706200	0	0	0
T50	0	13	0	0
T51	0	65	0	0
T52	0	76	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11931	0	0
T11	525748	1731	0	0
T13	0	1134	0	0
T32	0	32	0	0
T35	0	1716	0	0
T40	216162	0	0	0
T41	902871	0	0	0
T42	585414	0	0	0
T43	134922	0	0	0
T44	112216	0	0	0
T45	158941	0	0	0
T46	376435	0	0	0
T47	120130	0	0	0
T48	706200	0	0	0
T53	0	13	0	0
T54	0	4	0	0
T55	0	23	0	0
T56	0	109	0	0
T57	0	72	0	0
T58	0	8	0	0