Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1255874	0	0
cfg0_rd_A	2147483647	3253	0	0
compare_lower0_0_rd_A	2147483647	3256	0	0
compare_upper0_0_rd_A	2147483647	3200	0	0
ctrl_rd_A	2147483647	2991	0	0
intr_enable0_rd_A	2147483647	3924	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1255874	0	0
T13	975599	279500	0	0
T14	0	54424	0	0
T15	0	102259	0	0
T30	0	12	0	0
T31	0	4	0	0
T36	0	327727	0	0
T37	0	203026	0	0
T38	0	120573	0	0
T39	0	157240	0	0
T40	0	266	0	0
T41	359671	0	0	0
T42	194712	0	0	0
T43	430475	0	0	0
T44	188931	0	0	0
T45	793625	0	0	0
T46	206804	0	0	0
T47	131256	0	0	0
T48	508203	0	0	0
T49	115329	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3253	0	0
T14	223727	484	0	0
T30	0	187	0	0
T34	0	15	0	0
T39	0	1630	0	0
T50	0	13	0	0
T51	0	75	0	0
T52	0	9	0	0
T53	0	2	0	0
T54	0	22	0	0
T55	0	4	0	0
T56	126324	0	0	0
T57	313549	0	0	0
T58	352390	0	0	0
T59	231908	0	0	0
T60	137679	0	0	0
T61	596413	0	0	0
T62	355651	0	0	0
T63	332625	0	0	0
T64	760991	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3256	0	0
T14	223727	480	0	0
T30	0	104	0	0
T34	0	62	0	0
T39	0	1854	0	0
T50	0	6	0	0
T51	0	45	0	0
T52	0	10	0	0
T53	0	8	0	0
T54	0	7	0	0
T55	0	5	0	0
T56	126324	0	0	0
T57	313549	0	0	0
T58	352390	0	0	0
T59	231908	0	0	0
T60	137679	0	0	0
T61	596413	0	0	0
T62	355651	0	0	0
T63	332625	0	0	0
T64	760991	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3200	0	0
T14	223727	601	0	0
T30	0	130	0	0
T34	0	45	0	0
T39	0	1688	0	0
T50	0	12	0	0
T51	0	39	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	16	0	0
T55	0	13	0	0
T56	126324	0	0	0
T57	313549	0	0	0
T58	352390	0	0	0
T59	231908	0	0	0
T60	137679	0	0	0
T61	596413	0	0	0
T62	355651	0	0	0
T63	332625	0	0	0
T64	760991	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2991	0	0
T14	223727	513	0	0
T30	0	120	0	0
T34	0	40	0	0
T39	0	1614	0	0
T50	0	14	0	0
T51	0	35	0	0
T52	0	1	0	0
T54	0	14	0	0
T55	0	10	0	0
T56	126324	0	0	0
T57	313549	0	0	0
T58	352390	0	0	0
T59	231908	0	0	0
T60	137679	0	0	0
T61	596413	0	0	0
T62	355651	0	0	0
T63	332625	0	0	0
T64	760991	0	0	0
T65	0	94	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3924	0	0
T14	0	590	0	0
T17	5649	0	0	0
T61	0	17	0	0
T66	2126	17	0	0
T67	131311	36	0	0
T68	0	7	0	0
T69	0	49	0	0
T70	0	70	0	0
T71	0	51	0	0
T72	0	34	0	0
T73	0	14	0	0
T74	139781	0	0	0
T75	106809	0	0	0
T76	612688	0	0	0
T77	122288	0	0	0
T78	1826	0	0	0
T79	798462	0	0	0
T80	663019	0	0	0