Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2371653	0	0
cfg0_rd_A	2147483647	6958	0	0
compare_lower0_0_rd_A	2147483647	7332	0	0
compare_upper0_0_rd_A	2147483647	6178	0	0
ctrl_rd_A	2147483647	6478	0	0
intr_enable0_rd_A	2147483647	8314	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2371653	0	0
T1	128242	306469	0	0
T2	145569	0	0	0
T3	100853	0	0	0
T4	993658	0	0	0
T5	763500	0	0	0
T6	429217	0	0	0
T7	179205	0	0	0
T8	861211	0	0	0
T9	877054	0	0	0
T10	108957	0	0	0
T14	0	238397	0	0
T15	0	66116	0	0
T23	0	158814	0	0
T34	0	133941	0	0
T35	0	78419	0	0
T36	0	39810	0	0
T37	0	48549	0	0
T38	0	188417	0	0
T39	0	141175	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6958	0	0
T34	762322	1280	0	0
T35	294083	560	0	0
T37	0	488	0	0
T40	0	49	0	0
T41	0	378	0	0
T42	0	1238	0	0
T43	0	1082	0	0
T44	0	14	0	0
T45	0	11	0	0
T46	0	8	0	0
T47	595440	0	0	0
T48	312203	0	0	0
T49	360034	0	0	0
T50	179823	0	0	0
T51	321157	0	0	0
T52	900326	0	0	0
T53	314639	0	0	0
T54	154476	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7332	0	0
T34	762322	1351	0	0
T35	294083	550	0	0
T37	0	672	0	0
T40	0	80	0	0
T41	0	375	0	0
T42	0	1557	0	0
T43	0	1204	0	0
T44	0	6	0	0
T45	0	8	0	0
T46	0	2	0	0
T47	595440	0	0	0
T48	312203	0	0	0
T49	360034	0	0	0
T50	179823	0	0	0
T51	321157	0	0	0
T52	900326	0	0	0
T53	314639	0	0	0
T54	154476	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6178	0	0
T34	762322	1090	0	0
T35	294083	431	0	0
T37	0	469	0	0
T40	0	50	0	0
T41	0	332	0	0
T42	0	1148	0	0
T43	0	1009	0	0
T44	0	4	0	0
T45	0	12	0	0
T46	0	1	0	0
T47	595440	0	0	0
T48	312203	0	0	0
T49	360034	0	0	0
T50	179823	0	0	0
T51	321157	0	0	0
T52	900326	0	0	0
T53	314639	0	0	0
T54	154476	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6478	0	0
T34	762322	1309	0	0
T35	294083	497	0	0
T37	0	508	0	0
T40	0	49	0	0
T41	0	308	0	0
T42	0	1132	0	0
T43	0	1072	0	0
T44	0	1	0	0
T45	0	5	0	0
T46	0	7	0	0
T47	595440	0	0	0
T48	312203	0	0	0
T49	360034	0	0	0
T50	179823	0	0	0
T51	321157	0	0	0
T52	900326	0	0	0
T53	314639	0	0	0
T54	154476	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8314	0	0
T34	0	1624	0	0
T35	0	536	0	0
T37	0	730	0	0
T40	0	62	0	0
T55	368888	98	0	0
T56	0	35	0	0
T57	0	32	0	0
T58	0	27	0	0
T59	0	35	0	0
T60	0	34	0	0
T61	223683	0	0	0
T62	779819	0	0	0
T63	169127	0	0	0
T64	667355	0	0	0
T65	113918	0	0	0
T66	885269	0	0	0
T67	48178	0	0	0
T68	848027	0	0	0
T69	534109	0	0	0