Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1660354	0	0
cfg0_rd_A	2147483647	5735	0	0
compare_lower0_0_rd_A	2147483647	6053	0	0
compare_upper0_0_rd_A	2147483647	5283	0	0
ctrl_rd_A	2147483647	5264	0	0
intr_enable0_rd_A	2147483647	6805	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1660354	0	0
T13	665457	201914	0	0
T14	0	49558	0	0
T15	0	115202	0	0
T36	0	248585	0	0
T37	0	134592	0	0
T38	0	79726	0	0
T39	0	79074	0	0
T40	0	157864	0	0
T41	0	45224	0	0
T42	0	135254	0	0
T43	572970	0	0	0
T44	452277	0	0	0
T45	428870	0	0	0
T46	220026	0	0	0
T47	158976	0	0	0
T48	165375	0	0	0
T49	124929	0	0	0
T50	177225	0	0	0
T51	446586	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5735	0	0
T14	192735	493	0	0
T15	0	496	0	0
T36	0	1471	0	0
T37	0	747	0	0
T41	0	514	0	0
T52	0	42	0	0
T53	0	2	0	0
T54	0	119	0	0
T55	0	13	0	0
T56	0	11	0	0
T57	11122	0	0	0
T58	251855	0	0	0
T59	406867	0	0	0
T60	846744	0	0	0
T61	159141	0	0	0
T62	169160	0	0	0
T63	10580	0	0	0
T64	447030	0	0	0
T65	798919	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6053	0	0
T14	192735	585	0	0
T15	0	683	0	0
T36	0	1682	0	0
T37	0	794	0	0
T41	0	642	0	0
T52	0	37	0	0
T53	0	1	0	0
T54	0	129	0	0
T55	0	51	0	0
T56	0	3	0	0
T57	11122	0	0	0
T58	251855	0	0	0
T59	406867	0	0	0
T60	846744	0	0	0
T61	159141	0	0	0
T62	169160	0	0	0
T63	10580	0	0	0
T64	447030	0	0	0
T65	798919	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5283	0	0
T14	192735	495	0	0
T15	0	563	0	0
T36	0	1317	0	0
T37	0	700	0	0
T41	0	441	0	0
T52	0	83	0	0
T54	0	140	0	0
T55	0	49	0	0
T56	0	8	0	0
T57	11122	0	0	0
T58	251855	0	0	0
T59	406867	0	0	0
T60	846744	0	0	0
T61	159141	0	0	0
T62	169160	0	0	0
T63	10580	0	0	0
T64	447030	0	0	0
T65	798919	0	0	0
T66	0	114	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5264	0	0
T14	192735	504	0	0
T15	0	543	0	0
T36	0	1229	0	0
T37	0	768	0	0
T41	0	483	0	0
T52	0	26	0	0
T53	0	2	0	0
T54	0	156	0	0
T55	0	39	0	0
T56	0	13	0	0
T57	11122	0	0	0
T58	251855	0	0	0
T59	406867	0	0	0
T60	846744	0	0	0
T61	159141	0	0	0
T62	169160	0	0	0
T63	10580	0	0	0
T64	447030	0	0	0
T65	798919	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6805	0	0
T12	574257	80	0	0
T14	0	638	0	0
T15	0	729	0	0
T36	0	1664	0	0
T37	0	816	0	0
T46	0	19	0	0
T67	0	12	0	0
T68	0	27	0	0
T69	0	54	0	0
T70	0	7	0	0
T71	143378	0	0	0
T72	185404	0	0	0
T73	332403	0	0	0
T74	159000	0	0	0
T75	836535	0	0	0
T76	135631	0	0	0
T77	135873	0	0	0
T78	225589	0	0	0
T79	188184	0	0	0