Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1999665	0	0
cfg0_rd_A	2147483647	3045	0	0
compare_lower0_0_rd_A	2147483647	2727	0	0
compare_upper0_0_rd_A	2147483647	2547	0	0
ctrl_rd_A	2147483647	2663	0	0
intr_enable0_rd_A	2147483647	3699	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1999665	0	0
T13	175424	55584	0	0
T14	0	95279	0	0
T15	0	93854	0	0
T37	0	216890	0	0
T38	0	203249	0	0
T39	0	147143	0	0
T40	0	168289	0	0
T41	0	431093	0	0
T42	0	86656	0	0
T43	0	257404	0	0
T44	180302	0	0	0
T45	673867	0	0	0
T46	731351	0	0	0
T47	310192	0	0	0
T48	197349	0	0	0
T49	126347	0	0	0
T50	139687	0	0	0
T51	592487	0	0	0
T52	294912	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3045	0	0
T30	0	72	0	0
T31	0	71	0	0
T37	846105	1076	0	0
T53	0	7	0	0
T54	0	10	0	0
T55	0	14	0	0
T56	0	166	0	0
T57	0	115	0	0
T58	0	129	0	0
T59	0	63	0	0
T60	500005	0	0	0
T61	929193	0	0	0
T62	711858	0	0	0
T63	502229	0	0	0
T64	778871	0	0	0
T65	285193	0	0	0
T66	525734	0	0	0
T67	198619	0	0	0
T68	159801	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2727	0	0
T30	0	45	0	0
T31	0	44	0	0
T37	846105	1220	0	0
T55	0	12	0	0
T56	0	102	0	0
T57	0	66	0	0
T58	0	150	0	0
T59	0	49	0	0
T60	500005	0	0	0
T61	929193	0	0	0
T62	711858	0	0	0
T63	502229	0	0	0
T64	778871	0	0	0
T65	285193	0	0	0
T66	525734	0	0	0
T67	198619	0	0	0
T68	159801	0	0	0
T69	0	24	0	0
T70	0	52	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2547	0	0
T30	0	36	0	0
T31	0	37	0	0
T37	846105	1079	0	0
T55	0	3	0	0
T56	0	110	0	0
T57	0	74	0	0
T58	0	147	0	0
T59	0	60	0	0
T60	500005	0	0	0
T61	929193	0	0	0
T62	711858	0	0	0
T63	502229	0	0	0
T64	778871	0	0	0
T65	285193	0	0	0
T66	525734	0	0	0
T67	198619	0	0	0
T68	159801	0	0	0
T69	0	46	0	0
T70	0	73	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2663	0	0
T30	0	47	0	0
T31	0	66	0	0
T37	846105	1120	0	0
T55	0	2	0	0
T56	0	137	0	0
T57	0	58	0	0
T58	0	132	0	0
T59	0	63	0	0
T60	500005	0	0	0
T61	929193	0	0	0
T62	711858	0	0	0
T63	502229	0	0	0
T64	778871	0	0	0
T65	285193	0	0	0
T66	525734	0	0	0
T67	198619	0	0	0
T68	159801	0	0	0
T69	0	62	0	0
T70	0	104	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3699	0	0
T37	0	1302	0	0
T67	0	86	0	0
T71	429870	29	0	0
T72	0	68	0	0
T73	0	10	0	0
T74	0	35	0	0
T75	0	94	0	0
T76	0	31	0	0
T77	0	27	0	0
T78	0	12	0	0
T79	523171	0	0	0
T80	146539	0	0	0
T81	158432	0	0	0
T82	707030	0	0	0
T83	447814	0	0	0
T84	218888	0	0	0
T85	110437	0	0	0
T86	199208	0	0	0
T87	319886	0	0	0