Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2401274	0	0
cfg0_rd_A	2147483647	5396	0	0
compare_lower0_0_rd_A	2147483647	5855	0	0
compare_upper0_0_rd_A	2147483647	5300	0	0
ctrl_rd_A	2147483647	5035	0	0
intr_enable0_rd_A	2147483647	6498	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2401274	0	0
T13	858324	196246	0	0
T14	0	220531	0	0
T15	0	59363	0	0
T21	155153	0	0	0
T22	105226	0	0	0
T23	146203	0	0	0
T24	655274	0	0	0
T25	262143	0	0	0
T26	515075	0	0	0
T27	298670	0	0	0
T28	149316	0	0	0
T34	0	107776	0	0
T35	0	285890	0	0
T36	0	110401	0	0
T37	0	63055	0	0
T38	0	96830	0	0
T39	0	49835	0	0
T40	0	267750	0	0
T41	130471	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5396	0	0
T13	858324	1909	0	0
T15	0	533	0	0
T21	155153	0	0	0
T22	105226	0	0	0
T23	146203	0	0	0
T24	655274	0	0	0
T25	262143	0	0	0
T26	515075	0	0	0
T27	298670	0	0	0
T28	149316	0	0	0
T30	0	42	0	0
T31	0	31	0	0
T33	0	11	0	0
T37	0	654	0	0
T39	0	474	0	0
T41	130471	0	0	0
T42	0	1	0	0
T43	0	76	0	0
T44	0	37	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5855	0	0
T13	858324	2280	0	0
T15	0	737	0	0
T21	155153	0	0	0
T22	105226	0	0	0
T23	146203	0	0	0
T24	655274	0	0	0
T25	262143	0	0	0
T26	515075	0	0	0
T27	298670	0	0	0
T28	149316	0	0	0
T30	0	13	0	0
T31	0	59	0	0
T37	0	673	0	0
T39	0	482	0	0
T41	130471	0	0	0
T43	0	113	0	0
T44	0	18	0	0
T45	0	1	0	0
T46	0	86	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5300	0	0
T13	858324	2032	0	0
T15	0	599	0	0
T21	155153	0	0	0
T22	105226	0	0	0
T23	146203	0	0	0
T24	655274	0	0	0
T25	262143	0	0	0
T26	515075	0	0	0
T27	298670	0	0	0
T28	149316	0	0	0
T30	0	22	0	0
T31	0	36	0	0
T33	0	2	0	0
T37	0	632	0	0
T39	0	537	0	0
T41	130471	0	0	0
T42	0	3	0	0
T43	0	103	0	0
T45	0	16	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5035	0	0
T13	858324	1904	0	0
T15	0	634	0	0
T21	155153	0	0	0
T22	105226	0	0	0
T23	146203	0	0	0
T24	655274	0	0	0
T25	262143	0	0	0
T26	515075	0	0	0
T27	298670	0	0	0
T28	149316	0	0	0
T30	0	10	0	0
T31	0	42	0	0
T33	0	4	0	0
T37	0	671	0	0
T39	0	455	0	0
T41	130471	0	0	0
T43	0	33	0	0
T44	0	9	0	0
T45	0	4	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6498	0	0
T13	858324	2203	0	0
T15	0	618	0	0
T21	155153	0	0	0
T22	105226	0	0	0
T23	146203	0	0	0
T24	655274	0	0	0
T25	262143	0	0	0
T26	515075	0	0	0
T27	298670	0	0	0
T28	149316	0	0	0
T37	0	779	0	0
T41	130471	0	0	0
T47	0	20	0	0
T48	0	47	0	0
T49	0	10	0	0
T50	0	3	0	0
T51	0	56	0	0
T52	0	78	0	0
T53	0	11	0	0