Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66816300	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	68518352	1		T1	7866		T2	512450		T3	2535

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	133857454	1		T1	15685		T2	102556		T3	5091
values[0x0]	702177	1		T1	95		T2	42		T3	4
values[0x1]	775021	1		T1	90		T2	31		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53347723	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	81986929	1		T1	9446		T2	615733		T3	3038

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	435881	1		T1	54		T2	3923		T3	22
valid_sources[0x01]	435633	1		T1	53		T2	4096		T3	13
valid_sources[0x02]	435725	1		T1	53		T2	3963		T3	24
valid_sources[0x03]	434422	1		T1	56		T2	4082		T3	18
valid_sources[0x04]	438509	1		T1	58		T2	4063		T3	18
valid_sources[0x05]	645846	1		T1	74		T2	4056		T3	17
valid_sources[0x06]	535997	1		T1	59		T2	4075		T3	17
valid_sources[0x07]	435927	1		T1	68		T2	3999		T3	26
valid_sources[0x08]	846777	1		T1	62		T2	4049		T3	17
valid_sources[0x09]	434476	1		T1	61		T2	3818		T3	32
valid_sources[0x0a]	436843	1		T1	59		T2	4012		T3	22
valid_sources[0x0b]	432904	1		T1	64		T2	3948		T3	21
valid_sources[0x0c]	470677	1		T1	48		T2	3867		T3	22
valid_sources[0x0d]	447672	1		T1	71		T2	3986		T3	21
valid_sources[0x0e]	435783	1		T1	60		T2	3968		T3	25
valid_sources[0x0f]	429080	1		T1	54		T2	4010		T3	16
valid_sources[0x10]	434994	1		T1	57		T2	3962		T3	19
valid_sources[0x11]	492878	1		T1	67		T2	4016		T3	31
valid_sources[0x12]	432128	1		T1	49		T2	3987		T3	17
valid_sources[0x13]	433235	1		T1	76		T2	4096		T3	19
valid_sources[0x14]	430051	1		T1	74		T2	3942		T3	23
valid_sources[0x15]	447890	1		T1	69		T2	4004		T3	23
valid_sources[0x16]	436888	1		T1	61		T2	3955		T3	16
valid_sources[0x17]	433127	1		T1	66		T2	4093		T3	20
valid_sources[0x18]	434881	1		T1	52		T2	3857		T3	21
valid_sources[0x19]	435335	1		T1	55		T2	4051		T3	15
valid_sources[0x1a]	436964	1		T1	61		T2	4043		T3	18
valid_sources[0x1b]	429514	1		T1	61		T2	3959		T3	23
valid_sources[0x1c]	434688	1		T1	55		T2	3975		T3	18
valid_sources[0x1d]	434041	1		T1	56		T2	3959		T3	25
valid_sources[0x1e]	2038824	1		T1	56		T2	3936		T3	17
valid_sources[0x1f]	434816	1		T1	56		T2	4018		T3	20
valid_sources[0x20]	1080123	1		T1	65		T2	4053		T3	23
valid_sources[0x21]	433097	1		T1	67		T2	4175		T3	15
valid_sources[0x22]	436996	1		T1	58		T2	3956		T3	17
valid_sources[0x23]	434216	1		T1	59		T2	4102		T3	25
valid_sources[0x24]	445105	1		T1	51		T2	4013		T3	20
valid_sources[0x25]	433568	1		T1	60		T2	3871		T3	19
valid_sources[0x26]	433134	1		T1	64		T2	4135		T3	15
valid_sources[0x27]	437815	1		T1	50		T2	3977		T3	17
valid_sources[0x28]	433916	1		T1	54		T2	4062		T3	22
valid_sources[0x29]	484662	1		T1	55		T2	4045		T3	22
valid_sources[0x2a]	441507	1		T1	63		T2	4011		T3	30
valid_sources[0x2b]	441957	1		T1	65		T2	3976		T3	26
valid_sources[0x2c]	435720	1		T1	65		T2	3922		T3	17
valid_sources[0x2d]	437582	1		T1	72		T2	4099		T3	16
valid_sources[0x2e]	433293	1		T1	66		T2	4219		T3	22
valid_sources[0x2f]	432928	1		T1	40		T2	4020		T3	19
valid_sources[0x30]	437015	1		T1	60		T2	3877		T3	18
valid_sources[0x31]	436862	1		T1	62		T2	4229		T3	20
valid_sources[0x32]	432749	1		T1	52		T2	4064		T3	19
valid_sources[0x33]	487939	1		T1	68		T2	3907		T3	12
valid_sources[0x34]	472415	1		T1	62		T2	4147		T3	23
valid_sources[0x35]	434255	1		T1	69		T2	4041		T3	18
valid_sources[0x36]	1890528	1		T1	47		T2	3955		T3	25
valid_sources[0x37]	435849	1		T1	63		T2	4091		T3	21
valid_sources[0x38]	437846	1		T1	74		T2	3951		T3	21
valid_sources[0x39]	437427	1		T1	63		T2	4179		T3	23
valid_sources[0x3a]	437114	1		T1	64		T2	3914		T3	13
valid_sources[0x3b]	433610	1		T1	74		T2	4010		T3	16
valid_sources[0x3c]	435059	1		T1	62		T2	4095		T3	23
valid_sources[0x3d]	444788	1		T1	62		T2	4114		T3	24
valid_sources[0x3e]	605410	1		T1	53		T2	3940		T3	14
valid_sources[0x3f]	431403	1		T1	61		T2	4089		T3	12
valid_sources[0x40]	432876	1		T1	52		T2	3917		T3	13
valid_sources[0x41]	433643	1		T1	60		T2	3940		T3	22
valid_sources[0x42]	436354	1		T1	57		T2	4012		T3	21
valid_sources[0x43]	435892	1		T1	62		T2	3822		T3	16
valid_sources[0x44]	1260915	1		T1	67		T2	3836		T3	24
valid_sources[0x45]	438435	1		T1	70		T2	4172		T3	22
valid_sources[0x46]	431141	1		T1	73		T2	4196		T3	22
valid_sources[0x47]	432509	1		T1	78		T2	4122		T3	17
valid_sources[0x48]	433862	1		T1	57		T2	3993		T3	23
valid_sources[0x49]	696921	1		T1	46		T2	3985		T3	18
valid_sources[0x4a]	531961	1		T1	76		T2	4000		T3	25
valid_sources[0x4b]	481097	1		T1	65		T2	4149		T3	11
valid_sources[0x4c]	433321	1		T1	60		T2	3964		T3	18
valid_sources[0x4d]	434814	1		T1	57		T2	3992		T3	16
valid_sources[0x4e]	530141	1		T1	62		T2	3973		T3	19
valid_sources[0x4f]	436503	1		T1	70		T2	4139		T3	21
valid_sources[0x50]	443852	1		T1	63		T2	3908		T3	15
valid_sources[0x51]	434448	1		T1	72		T2	3874		T3	23
valid_sources[0x52]	434480	1		T1	79		T2	3983		T3	9
valid_sources[0x53]	433324	1		T1	61		T2	3767		T3	23
valid_sources[0x54]	560108	1		T1	70		T2	3936		T3	21
valid_sources[0x55]	434634	1		T1	61		T2	3864		T3	31
valid_sources[0x56]	433050	1		T1	59		T2	3923		T3	21
valid_sources[0x57]	438048	1		T1	63		T2	4116		T3	14
valid_sources[0x58]	432166	1		T1	64		T2	3958		T3	18
valid_sources[0x59]	433817	1		T1	57		T2	4092		T3	28
valid_sources[0x5a]	434519	1		T1	65		T2	4081		T3	32
valid_sources[0x5b]	437838	1		T1	67		T2	4040		T3	18
valid_sources[0x5c]	508184	1		T1	61		T2	4085		T3	35
valid_sources[0x5d]	433725	1		T1	61		T2	4102		T3	20
valid_sources[0x5e]	436708	1		T1	52		T2	3764		T3	24
valid_sources[0x5f]	440232	1		T1	56		T2	4091		T3	21
valid_sources[0x60]	441281	1		T1	80		T2	4244		T3	21
valid_sources[0x61]	434006	1		T1	47		T2	3965		T3	30
valid_sources[0x62]	435914	1		T1	63		T2	3921		T3	21
valid_sources[0x63]	431848	1		T1	68		T2	4026		T3	30
valid_sources[0x64]	465479	1		T1	49		T2	3930		T3	21
valid_sources[0x65]	431799	1		T1	51		T2	3970		T3	15
valid_sources[0x66]	438170	1		T1	63		T2	3886		T3	15
valid_sources[0x67]	503293	1		T1	68		T2	4034		T3	18
valid_sources[0x68]	433684	1		T1	70		T2	4023		T3	11
valid_sources[0x69]	435264	1		T1	60		T2	4066		T3	17
valid_sources[0x6a]	432855	1		T1	67		T2	4036		T3	21
valid_sources[0x6b]	648404	1		T1	58		T2	3724		T3	22
valid_sources[0x6c]	436173	1		T1	54		T2	4295		T3	19
valid_sources[0x6d]	605345	1		T1	70		T2	3947		T3	18
valid_sources[0x6e]	434910	1		T1	54		T2	4137		T3	18
valid_sources[0x6f]	434677	1		T1	61		T2	4041		T3	23
valid_sources[0x70]	2134306	1		T1	57		T2	4058		T3	14
valid_sources[0x71]	435904	1		T1	51		T2	3966		T3	15
valid_sources[0x72]	705845	1		T1	59		T2	3968		T3	25
valid_sources[0x73]	432852	1		T1	52		T2	3983		T3	11
valid_sources[0x74]	445757	1		T1	64		T2	4096		T3	20
valid_sources[0x75]	430023	1		T1	77		T2	4091		T3	36
valid_sources[0x76]	1009960	1		T1	74		T2	4125		T3	17
valid_sources[0x77]	545314	1		T1	52		T2	4095		T3	21
valid_sources[0x78]	433931	1		T1	51		T2	4208		T3	24
valid_sources[0x79]	432641	1		T1	72		T2	3999		T3	21
valid_sources[0x7a]	431766	1		T1	67		T2	4034		T3	22
valid_sources[0x7b]	1086876	1		T1	48		T2	4051		T3	18
valid_sources[0x7c]	448272	1		T1	73		T2	3940		T3	23
valid_sources[0x7d]	434377	1		T1	50		T2	4036		T3	22
valid_sources[0x7e]	435596	1		T1	77		T2	4001		T3	20
valid_sources[0x7f]	433405	1		T1	76		T2	3923		T3	24
valid_sources[0x80]	437935	1		T1	54		T2	4002		T3	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67140962

1

T1

7803

T2

512391

T3

2522

values[0x0]

all_enables

biggest_size

689428

1

T1

41

T2

37

T3

3

values[0x1]

all_enables

biggest_size

687962

1

T1

22

T2

22

T3

10