Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2406348	0	0
cfg0_rd_A	2147483647	2647	0	0
compare_lower0_0_rd_A	2147483647	2299	0	0
compare_upper0_0_rd_A	2147483647	2080	0	0
ctrl_rd_A	2147483647	2053	0	0
intr_enable0_rd_A	2147483647	3274	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2406348	0	0
T11	504775	215711	0	0
T12	195402	78893	0	0
T13	0	42899	0	0
T14	7841	0	0	0
T19	126717	0	0	0
T20	46271	0	0	0
T21	681970	0	0	0
T22	260628	0	0	0
T23	498858	0	0	0
T33	0	345569	0	0
T34	0	97540	0	0
T35	0	150878	0	0
T36	0	261129	0	0
T37	0	46853	0	0
T38	0	183316	0	0
T39	0	300074	0	0
T40	862966	0	0	0
T41	601966	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2647	0	0
T28	0	37	0	0
T29	0	184	0	0
T32	0	44	0	0
T42	694987	397	0	0
T43	0	19	0	0
T44	0	21	0	0
T45	0	4	0	0
T46	0	10	0	0
T47	0	37	0	0
T48	0	34	0	0
T49	518644	0	0	0
T50	171195	0	0	0
T51	668591	0	0	0
T52	322277	0	0	0
T53	375494	0	0	0
T54	107082	0	0	0
T55	107720	0	0	0
T56	429205	0	0	0
T57	352528	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2299	0	0
T28	0	21	0	0
T29	0	80	0	0
T32	0	13	0	0
T42	694987	475	0	0
T43	0	13	0	0
T44	0	16	0	0
T45	0	11	0	0
T46	0	2	0	0
T47	0	19	0	0
T49	518644	0	0	0
T50	171195	0	0	0
T51	668591	0	0	0
T52	322277	0	0	0
T53	375494	0	0	0
T54	107082	0	0	0
T55	107720	0	0	0
T56	429205	0	0	0
T57	352528	0	0	0
T58	0	2	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2080	0	0
T28	0	17	0	0
T29	0	100	0	0
T32	0	21	0	0
T42	694987	382	0	0
T43	0	32	0	0
T44	0	11	0	0
T45	0	12	0	0
T46	0	8	0	0
T47	0	23	0	0
T48	0	41	0	0
T49	518644	0	0	0
T50	171195	0	0	0
T51	668591	0	0	0
T52	322277	0	0	0
T53	375494	0	0	0
T54	107082	0	0	0
T55	107720	0	0	0
T56	429205	0	0	0
T57	352528	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2053	0	0
T28	0	25	0	0
T29	0	131	0	0
T32	0	17	0	0
T42	694987	358	0	0
T43	0	14	0	0
T44	0	15	0	0
T45	0	6	0	0
T46	0	5	0	0
T47	0	25	0	0
T48	0	35	0	0
T49	518644	0	0	0
T50	171195	0	0	0
T51	668591	0	0	0
T52	322277	0	0	0
T53	375494	0	0	0
T54	107082	0	0	0
T55	107720	0	0	0
T56	429205	0	0	0
T57	352528	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3274	0	0
T6	466567	78	0	0
T7	162412	0	0	0
T8	513455	0	0	0
T9	991016	0	0	0
T10	467137	0	0	0
T11	504775	0	0	0
T14	7841	0	0	0
T40	862966	0	0	0
T41	601966	0	0	0
T42	0	415	0	0
T53	0	64	0	0
T59	0	52	0	0
T60	0	110	0	0
T61	0	65	0	0
T62	0	36	0	0
T63	0	47	0	0
T64	0	11	0	0
T65	0	76	0	0
T66	298535	0	0	0