Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2448996	0	0
cfg0_rd_A	2147483647	6219	0	0
compare_lower0_0_rd_A	2147483647	6619	0	0
compare_upper0_0_rd_A	2147483647	6107	0	0
ctrl_rd_A	2147483647	5998	0	0
intr_enable0_rd_A	2147483647	7879	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2448996	0	0
T15	134276	570437	0	0
T16	0	12528	0	0
T17	0	283837	0	0
T37	0	106992	0	0
T38	0	109709	0	0
T39	0	130240	0	0
T40	0	162597	0	0
T41	0	26745	0	0
T42	0	86017	0	0
T43	0	43457	0	0
T44	431249	0	0	0
T45	612106	0	0	0
T46	174748	0	0	0
T47	139541	0	0	0
T48	119517	0	0	0
T49	149674	0	0	0
T50	828978	0	0	0
T51	110442	0	0	0
T52	207457	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6219	0	0
T34	0	143	0	0
T38	419388	1034	0	0
T41	0	325	0	0
T43	0	498	0	0
T53	0	1176	0	0
T54	0	1527	0	0
T55	0	32	0	0
T56	0	14	0	0
T57	0	6	0	0
T58	0	10	0	0
T59	509418	0	0	0
T60	424093	0	0	0
T61	175213	0	0	0
T62	142065	0	0	0
T63	100679	0	0	0
T64	102160	0	0	0
T65	139432	0	0	0
T66	122355	0	0	0
T67	138377	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6619	0	0
T38	419388	1230	0	0
T41	0	382	0	0
T43	0	574	0	0
T53	0	1273	0	0
T54	0	1641	0	0
T55	0	25	0	0
T56	0	12	0	0
T57	0	2	0	0
T59	509418	0	0	0
T60	424093	0	0	0
T61	175213	0	0	0
T62	142065	0	0	0
T63	100679	0	0	0
T64	102160	0	0	0
T65	139432	0	0	0
T66	122355	0	0	0
T67	138377	0	0	0
T68	0	9	0	0
T69	0	7	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6107	0	0
T34	0	82	0	0
T38	419388	1150	0	0
T41	0	286	0	0
T43	0	445	0	0
T53	0	1064	0	0
T54	0	1705	0	0
T55	0	20	0	0
T56	0	11	0	0
T59	509418	0	0	0
T60	424093	0	0	0
T61	175213	0	0	0
T62	142065	0	0	0
T63	100679	0	0	0
T64	102160	0	0	0
T65	139432	0	0	0
T66	122355	0	0	0
T67	138377	0	0	0
T68	0	23	0	0
T69	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5998	0	0
T38	419388	1188	0	0
T41	0	309	0	0
T43	0	441	0	0
T53	0	1028	0	0
T54	0	1577	0	0
T55	0	34	0	0
T56	0	1	0	0
T57	0	7	0	0
T59	509418	0	0	0
T60	424093	0	0	0
T61	175213	0	0	0
T62	142065	0	0	0
T63	100679	0	0	0
T64	102160	0	0	0
T65	139432	0	0	0
T66	122355	0	0	0
T67	138377	0	0	0
T68	0	11	0	0
T70	0	2	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7879	0	0
T38	0	1407	0	0
T41	0	418	0	0
T71	193427	50	0	0
T72	590831	5	0	0
T73	0	24	0	0
T74	0	33	0	0
T75	0	56	0	0
T76	0	27	0	0
T77	0	20	0	0
T78	0	72	0	0
T79	117226	0	0	0
T80	142058	0	0	0
T81	771636	0	0	0
T82	126695	0	0	0
T83	119042	0	0	0
T84	150855	0	0	0
T85	873832	0	0	0
T86	139891	0	0	0