Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64016905	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	64489902	1		T1	3777		T2	159547		T3	40582

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	128082910	1		T1	7618		T2	319357		T3	81166
values[0x0]	202374	1		T1	5		T2	26		T3	32
values[0x1]	221523	1		T1	5		T2	31		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51149177	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	77357630	1		T1	4557		T2	191370		T3	48850

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	345404	1		T2	1227		T3	344		T5	8
valid_sources[0x01]	2370501	1		T2	1257		T3	324		T5	7
valid_sources[0x02]	353872	1		T2	1226		T3	328		T5	9
valid_sources[0x03]	347985	1		T2	1255		T3	322		T5	9
valid_sources[0x04]	690080	1		T2	1261		T3	313		T5	12
valid_sources[0x05]	342765	1		T2	1297		T3	313		T5	8
valid_sources[0x06]	348703	1		T2	1275		T3	307		T5	14
valid_sources[0x07]	345067	1		T2	1276		T3	332		T5	7
valid_sources[0x08]	345487	1		T2	1226		T3	279		T5	7
valid_sources[0x09]	346630	1		T2	1232		T3	305		T5	9
valid_sources[0x0a]	348697	1		T2	1263		T3	300		T5	5
valid_sources[0x0b]	347474	1		T2	1315		T3	331		T5	10
valid_sources[0x0c]	342539	1		T2	1244		T3	314		T5	11
valid_sources[0x0d]	2299217	1		T2	1222		T3	324		T5	7
valid_sources[0x0e]	346813	1		T2	1349		T3	300		T5	12
valid_sources[0x0f]	342399	1		T2	1325		T3	338		T5	5
valid_sources[0x10]	384791	1		T2	1300		T3	321		T5	6
valid_sources[0x11]	344705	1		T2	1289		T3	294		T5	12
valid_sources[0x12]	343527	1		T2	1259		T3	257		T5	6
valid_sources[0x13]	1026620	1		T2	1297		T3	299		T5	3
valid_sources[0x14]	385558	1		T2	1289		T3	357		T5	8
valid_sources[0x15]	345708	1		T2	1297		T3	330		T5	11
valid_sources[0x16]	343647	1		T2	1258		T3	344		T5	8
valid_sources[0x17]	346123	1		T2	1247		T3	268		T5	3
valid_sources[0x18]	344776	1		T2	1243		T3	310		T5	8
valid_sources[0x19]	351388	1		T2	1241		T3	315		T5	7
valid_sources[0x1a]	799927	1		T2	1250		T3	323		T5	7
valid_sources[0x1b]	342602	1		T2	1228		T3	275		T5	7
valid_sources[0x1c]	341634	1		T2	1249		T3	319		T5	6
valid_sources[0x1d]	345424	1		T2	1232		T3	310		T5	5
valid_sources[0x1e]	345390	1		T2	1197		T3	337		T5	6
valid_sources[0x1f]	648440	1		T2	1170		T3	332		T5	7
valid_sources[0x20]	345310	1		T2	1202		T3	315		T5	8
valid_sources[0x21]	345221	1		T2	1231		T3	336		T5	9
valid_sources[0x22]	918999	1		T2	1245		T3	306		T5	9
valid_sources[0x23]	346487	1		T2	1232		T3	330		T5	10
valid_sources[0x24]	344832	1		T2	1279		T3	301		T5	4
valid_sources[0x25]	342872	1		T2	1210		T3	304		T5	9
valid_sources[0x26]	2609317	1		T2	1307		T3	322		T5	8
valid_sources[0x27]	1749042	1		T2	1253		T3	308		T5	5
valid_sources[0x28]	346593	1		T2	1318		T3	305		T5	8
valid_sources[0x29]	341792	1		T2	1233		T3	265		T5	2
valid_sources[0x2a]	996689	1		T2	1278		T3	331		T5	7
valid_sources[0x2b]	347230	1		T2	1191		T3	312		T5	4
valid_sources[0x2c]	346965	1		T2	1213		T3	300		T5	9
valid_sources[0x2d]	1372219	1		T2	1227		T3	311		T5	7
valid_sources[0x2e]	346254	1		T2	1165		T3	322		T5	5
valid_sources[0x2f]	345334	1		T2	1219		T3	307		T5	2
valid_sources[0x30]	348118	1		T2	1317		T3	295		T5	11
valid_sources[0x31]	348926	1		T2	1259		T3	283		T5	5
valid_sources[0x32]	344711	1		T2	1235		T3	329		T5	11
valid_sources[0x33]	392101	1		T2	1290		T3	316		T5	17
valid_sources[0x34]	629641	1		T2	1248		T3	364		T5	7
valid_sources[0x35]	352572	1		T2	1233		T3	320		T5	4
valid_sources[0x36]	352231	1		T2	1225		T3	318		T5	5
valid_sources[0x37]	362362	1		T2	1281		T3	283		T5	6
valid_sources[0x38]	344283	1		T2	1207		T3	348		T5	8
valid_sources[0x39]	343851	1		T2	1276		T3	326		T5	7
valid_sources[0x3a]	343681	1		T2	1221		T3	350		T5	5
valid_sources[0x3b]	431963	1		T2	1260		T3	367		T5	6
valid_sources[0x3c]	349297	1		T2	1204		T3	346		T5	4
valid_sources[0x3d]	350165	1		T2	1271		T3	331		T5	11
valid_sources[0x3e]	564203	1		T2	1249		T3	330		T5	5
valid_sources[0x3f]	345694	1		T2	1272		T3	298		T5	5
valid_sources[0x40]	1573348	1		T2	1206		T3	314		T5	4
valid_sources[0x41]	573671	1		T2	1274		T3	288		T5	5
valid_sources[0x42]	344578	1		T2	1263		T3	301		T5	6
valid_sources[0x43]	345783	1		T2	1234		T3	305		T5	12
valid_sources[0x44]	356168	1		T2	1246		T3	307		T5	11
valid_sources[0x45]	346177	1		T2	1254		T3	344		T5	5
valid_sources[0x46]	369012	1		T2	1255		T3	313		T5	5
valid_sources[0x47]	343761	1		T2	1218		T3	324		T5	10
valid_sources[0x48]	342665	1		T2	1276		T3	331		T5	7
valid_sources[0x49]	349251	1		T2	1244		T3	317		T5	11
valid_sources[0x4a]	347585	1		T2	1286		T3	361		T5	8
valid_sources[0x4b]	348029	1		T2	1311		T3	368		T5	9
valid_sources[0x4c]	346485	1		T2	1152		T3	328		T5	8
valid_sources[0x4d]	2028682	1		T2	1241		T3	306		T5	5
valid_sources[0x4e]	348017	1		T2	1271		T3	263		T5	7
valid_sources[0x4f]	589970	1		T2	1284		T3	365		T5	12
valid_sources[0x50]	343536	1		T2	1229		T3	349		T5	8
valid_sources[0x51]	345202	1		T2	1230		T3	314		T5	7
valid_sources[0x52]	366308	1		T2	1267		T3	354		T5	5
valid_sources[0x53]	343214	1		T2	1232		T3	321		T5	9
valid_sources[0x54]	348960	1		T2	1294		T3	287		T5	5
valid_sources[0x55]	344636	1		T2	1195		T3	326		T5	20
valid_sources[0x56]	345005	1		T2	1284		T3	260		T5	10
valid_sources[0x57]	361863	1		T2	1267		T3	332		T5	4
valid_sources[0x58]	342980	1		T2	1200		T3	338		T5	3
valid_sources[0x59]	345593	1		T2	1290		T3	329		T5	8
valid_sources[0x5a]	1262939	1		T2	1250		T3	312		T5	8
valid_sources[0x5b]	346164	1		T2	1170		T3	348		T5	15
valid_sources[0x5c]	344183	1		T2	1240		T3	290		T5	8
valid_sources[0x5d]	349917	1		T2	1226		T3	315		T5	8
valid_sources[0x5e]	344963	1		T2	1346		T3	299		T5	9
valid_sources[0x5f]	346774	1		T2	1229		T3	326		T5	4
valid_sources[0x60]	347986	1		T2	1262		T3	306		T5	6
valid_sources[0x61]	346340	1		T2	1205		T3	316		T5	7
valid_sources[0x62]	349577	1		T2	1223		T3	329		T5	4
valid_sources[0x63]	346556	1		T2	1264		T3	337		T5	8
valid_sources[0x64]	369217	1		T2	1255		T3	311		T5	6
valid_sources[0x65]	342795	1		T2	1302		T3	317		T5	9
valid_sources[0x66]	345042	1		T2	1191		T3	299		T5	8
valid_sources[0x67]	344409	1		T2	1274		T3	296		T5	6
valid_sources[0x68]	345341	1		T2	1277		T3	332		T5	5
valid_sources[0x69]	348874	1		T2	1212		T3	350		T5	7
valid_sources[0x6a]	347564	1		T2	1161		T3	326		T5	6
valid_sources[0x6b]	345211	1		T2	1247		T3	300		T5	1
valid_sources[0x6c]	343906	1		T2	1258		T3	321		T5	11
valid_sources[0x6d]	399790	1		T2	1353		T3	347		T5	5
valid_sources[0x6e]	348346	1		T2	1190		T3	296		T5	5
valid_sources[0x6f]	476631	1		T2	1231		T3	303		T5	8
valid_sources[0x70]	348822	1		T2	1261		T3	288		T5	4
valid_sources[0x71]	344214	1		T2	1217		T3	297		T5	8
valid_sources[0x72]	355150	1		T2	1231		T3	269		T5	3
valid_sources[0x73]	341636	1		T2	1264		T3	341		T5	6
valid_sources[0x74]	348979	1		T2	1237		T3	307		T5	12
valid_sources[0x75]	342090	1		T2	1170		T3	355		T5	7
valid_sources[0x76]	344434	1		T2	1223		T3	317		T5	7
valid_sources[0x77]	344358	1		T2	1273		T3	324		T5	8
valid_sources[0x78]	347166	1		T2	1200		T3	310		T5	12
valid_sources[0x79]	341900	1		T2	1281		T3	287		T5	15
valid_sources[0x7a]	358294	1		T2	1237		T3	280		T5	6
valid_sources[0x7b]	374571	1		T2	1210		T3	327		T5	7
valid_sources[0x7c]	345753	1		T2	1276		T3	326		T5	11
valid_sources[0x7d]	345280	1		T2	1233		T3	343		T5	12
valid_sources[0x7e]	404456	1		T2	1228		T3	288		T5	10
valid_sources[0x7f]	346135	1		T2	1298		T3	283		T5	6
valid_sources[0x80]	477936	1		T2	1293		T3	372		T5	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64099872

1

T1

3771

T2

159509

T3

40541

values[0x0]

all_enables

biggest_size

195742

1

T1

4

T2

20

T3

28

values[0x1]

all_enables

biggest_size

194288

1

T1

2

T2

18

T3

13