Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	631418	0	0
cfg0_rd_A	2147483647	5529	0	0
compare_lower0_0_rd_A	2147483647	5784	0	0
compare_upper0_0_rd_A	2147483647	5184	0	0
ctrl_rd_A	2147483647	4887	0	0
intr_enable0_rd_A	2147483647	6366	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	631418	0	0
T12	624601	27146	0	0
T13	0	96471	0	0
T14	0	111849	0	0
T15	3428	0	0	0
T23	412303	0	0	0
T24	227089	0	0	0
T25	131335	0	0	0
T29	0	9	0	0
T32	0	50610	0	0
T33	0	32053	0	0
T34	0	73517	0	0
T35	0	70307	0	0
T36	0	90520	0	0
T37	0	66527	0	0
T38	126958	0	0	0
T39	193367	0	0	0
T40	455869	0	0	0
T41	121462	0	0	0
T42	239752	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5529	0	0
T13	423764	1016	0	0
T26	0	63	0	0
T28	0	101	0	0
T29	0	13	0	0
T31	0	23	0	0
T32	0	609	0	0
T33	0	310	0	0
T34	0	770	0	0
T35	0	725	0	0
T43	0	7	0	0
T44	809950	0	0	0
T45	877723	0	0	0
T46	249199	0	0	0
T47	17253	0	0	0
T48	522679	0	0	0
T49	755902	0	0	0
T50	128787	0	0	0
T51	8302	0	0	0
T52	194288	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5784	0	0
T13	423764	1130	0	0
T26	0	20	0	0
T28	0	73	0	0
T29	0	12	0	0
T31	0	4	0	0
T32	0	651	0	0
T33	0	360	0	0
T34	0	866	0	0
T35	0	828	0	0
T43	0	7	0	0
T44	809950	0	0	0
T45	877723	0	0	0
T46	249199	0	0	0
T47	17253	0	0	0
T48	522679	0	0	0
T49	755902	0	0	0
T50	128787	0	0	0
T51	8302	0	0	0
T52	194288	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5184	0	0
T13	423764	987	0	0
T26	0	41	0	0
T28	0	96	0	0
T29	0	8	0	0
T31	0	20	0	0
T32	0	488	0	0
T33	0	343	0	0
T34	0	774	0	0
T35	0	719	0	0
T43	0	2	0	0
T44	809950	0	0	0
T45	877723	0	0	0
T46	249199	0	0	0
T47	17253	0	0	0
T48	522679	0	0	0
T49	755902	0	0	0
T50	128787	0	0	0
T51	8302	0	0	0
T52	194288	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4887	0	0
T13	423764	811	0	0
T26	0	30	0	0
T28	0	60	0	0
T29	0	1	0	0
T31	0	17	0	0
T32	0	468	0	0
T33	0	321	0	0
T34	0	772	0	0
T35	0	720	0	0
T43	0	1	0	0
T44	809950	0	0	0
T45	877723	0	0	0
T46	249199	0	0	0
T47	17253	0	0	0
T48	522679	0	0	0
T49	755902	0	0	0
T50	128787	0	0	0
T51	8302	0	0	0
T52	194288	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6366	0	0
T13	0	1078	0	0
T23	412303	20	0	0
T24	227089	0	0	0
T25	131335	0	0	0
T32	0	670	0	0
T33	0	370	0	0
T38	126958	0	0	0
T39	193367	0	0	0
T40	455869	0	0	0
T41	121462	0	0	0
T42	239752	0	0	0
T53	0	81	0	0
T54	0	13	0	0
T55	0	37	0	0
T56	0	48	0	0
T57	0	7	0	0
T58	0	12	0	0
T59	167484	0	0	0
T60	19877	0	0	0