Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2346489	0	0
cfg0_rd_A	2147483647	9738	0	0
compare_lower0_0_rd_A	2147483647	10719	0	0
compare_upper0_0_rd_A	2147483647	9606	0	0
ctrl_rd_A	2147483647	8789	0	0
intr_enable0_rd_A	2147483647	12277	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2346489	0	0
T11	509092	102223	0	0
T12	0	112564	0	0
T13	0	7019	0	0
T33	0	93684	0	0
T34	0	268133	0	0
T35	0	350127	0	0
T36	0	201958	0	0
T37	0	380817	0	0
T38	0	172433	0	0
T39	0	77010	0	0
T40	361463	0	0	0
T41	551581	0	0	0
T42	113372	0	0	0
T43	179105	0	0	0
T44	394178	0	0	0
T45	294699	0	0	0
T46	468922	0	0	0
T47	420654	0	0	0
T48	129002	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9738	0	0
T34	123653	2644	0	0
T35	0	1871	0	0
T38	0	1801	0	0
T49	0	406	0	0
T50	0	842	0	0
T51	0	1010	0	0
T52	0	80	0	0
T53	0	17	0	0
T54	0	99	0	0
T55	0	38	0	0
T56	433680	0	0	0
T57	301523	0	0	0
T58	404095	0	0	0
T59	169657	0	0	0
T60	237776	0	0	0
T61	744231	0	0	0
T62	121411	0	0	0
T63	1213	0	0	0
T64	363540	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10719	0	0
T34	123653	3167	0	0
T35	0	2133	0	0
T38	0	1971	0	0
T49	0	487	0	0
T50	0	842	0	0
T51	0	1227	0	0
T52	0	65	0	0
T53	0	9	0	0
T54	0	101	0	0
T55	0	16	0	0
T56	433680	0	0	0
T57	301523	0	0	0
T58	404095	0	0	0
T59	169657	0	0	0
T60	237776	0	0	0
T61	744231	0	0	0
T62	121411	0	0	0
T63	1213	0	0	0
T64	363540	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9606	0	0
T34	123653	2727	0	0
T35	0	2040	0	0
T38	0	1747	0	0
T49	0	416	0	0
T50	0	763	0	0
T51	0	1036	0	0
T52	0	52	0	0
T54	0	76	0	0
T55	0	18	0	0
T56	433680	0	0	0
T57	301523	0	0	0
T58	404095	0	0	0
T59	169657	0	0	0
T60	237776	0	0	0
T61	744231	0	0	0
T62	121411	0	0	0
T63	1213	0	0	0
T64	363540	0	0	0
T65	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8789	0	0
T34	123653	2494	0	0
T35	0	1897	0	0
T38	0	1497	0	0
T49	0	364	0	0
T50	0	755	0	0
T51	0	920	0	0
T52	0	88	0	0
T53	0	9	0	0
T54	0	66	0	0
T55	0	25	0	0
T56	433680	0	0	0
T57	301523	0	0	0
T58	404095	0	0	0
T59	169657	0	0	0
T60	237776	0	0	0
T61	744231	0	0	0
T62	121411	0	0	0
T63	1213	0	0	0
T64	363540	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12277	0	0
T7	102543	116	0	0
T8	135928	0	0	0
T9	690992	0	0	0
T10	421047	0	0	0
T21	0	35	0	0
T34	0	3362	0	0
T35	0	2098	0	0
T38	0	2157	0	0
T66	0	21	0	0
T67	0	32	0	0
T68	0	56	0	0
T69	0	11	0	0
T70	0	66	0	0
T71	150532	0	0	0
T72	112776	0	0	0
T73	413038	0	0	0
T74	932444	0	0	0
T75	137288	0	0	0
T76	430004	0	0	0