Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2216329	0	0
cfg0_rd_A	2147483647	10153	0	0
compare_lower0_0_rd_A	2147483647	10830	0	0
compare_upper0_0_rd_A	2147483647	9806	0	0
ctrl_rd_A	2147483647	9327	0	0
intr_enable0_rd_A	2147483647	11883	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2216329	0	0
T14	444373	172597	0	0
T15	612623	170464	0	0
T16	350709	146791	0	0
T27	108767	0	0	0
T28	148740	0	0	0
T36	0	107085	0	0
T37	0	131018	0	0
T38	0	175921	0	0
T39	0	27955	0	0
T40	0	157197	0	0
T41	0	136437	0	0
T42	0	160489	0	0
T43	1918	0	0	0
T44	58605	0	0	0
T45	593391	0	0	0
T46	169934	0	0	0
T47	144482	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10153	0	0
T34	0	12	0	0
T35	0	23	0	0
T36	692486	587	0	0
T37	0	1554	0	0
T39	0	244	0	0
T40	0	1500	0	0
T42	0	1551	0	0
T48	0	1607	0	0
T49	0	940	0	0
T50	0	28	0	0
T51	106637	0	0	0
T52	220536	0	0	0
T53	100889	0	0	0
T54	870124	0	0	0
T55	486307	0	0	0
T56	514256	0	0	0
T57	270370	0	0	0
T58	647347	0	0	0
T59	178539	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10830	0	0
T34	0	1	0	0
T35	0	81	0	0
T36	692486	632	0	0
T37	0	1525	0	0
T39	0	341	0	0
T40	0	1695	0	0
T42	0	1796	0	0
T48	0	1757	0	0
T49	0	1253	0	0
T50	0	81	0	0
T51	106637	0	0	0
T52	220536	0	0	0
T53	100889	0	0	0
T54	870124	0	0	0
T55	486307	0	0	0
T56	514256	0	0	0
T57	270370	0	0	0
T58	647347	0	0	0
T59	178539	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9806	0	0
T34	0	10	0	0
T35	0	47	0	0
T36	692486	502	0	0
T37	0	1291	0	0
T39	0	263	0	0
T40	0	1639	0	0
T42	0	1619	0	0
T48	0	1437	0	0
T49	0	1223	0	0
T51	106637	0	0	0
T52	220536	0	0	0
T53	100889	0	0	0
T54	870124	0	0	0
T55	486307	0	0	0
T56	514256	0	0	0
T57	270370	0	0	0
T58	647347	0	0	0
T59	178539	0	0	0
T60	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9327	0	0
T34	0	11	0	0
T35	0	58	0	0
T36	692486	604	0	0
T37	0	1214	0	0
T39	0	298	0	0
T40	0	1417	0	0
T42	0	1507	0	0
T48	0	1659	0	0
T49	0	857	0	0
T50	0	64	0	0
T51	106637	0	0	0
T52	220536	0	0	0
T53	100889	0	0	0
T54	870124	0	0	0
T55	486307	0	0	0
T56	514256	0	0	0
T57	270370	0	0	0
T58	647347	0	0	0
T59	178539	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11883	0	0
T36	692486	633	0	0
T37	0	1427	0	0
T39	0	353	0	0
T40	0	1673	0	0
T51	106637	0	0	0
T52	220536	0	0	0
T53	100889	0	0	0
T54	870124	0	0	0
T55	486307	0	0	0
T56	514256	0	0	0
T57	270370	0	0	0
T58	647347	0	0	0
T59	178539	0	0	0
T61	0	93	0	0
T62	0	96	0	0
T63	0	54	0	0
T64	0	117	0	0
T65	0	59	0	0
T66	0	37	0	0