Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68073862	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	69711620	1		T1	10174		T2	17262		T3	93757

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136375056	1		T1	20187		T2	34246		T3	187907
values[0x0]	671649	1		T1	56		T2	25		T3	16
values[0x1]	738777	1		T1	50		T2	36		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54361240	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	83424242	1		T1	12141		T2	20701		T3	112734

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	399067	1		T1	73		T3	739		T4	124
valid_sources[0x01]	402546	1		T1	54		T3	727		T4	126
valid_sources[0x02]	515932	1		T1	84		T3	789		T4	138
valid_sources[0x03]	403394	1		T1	59		T3	667		T4	148
valid_sources[0x04]	400220	1		T1	87		T3	770		T4	178
valid_sources[0x05]	403214	1		T1	53		T3	730		T4	137
valid_sources[0x06]	404477	1		T1	79		T3	762		T4	129
valid_sources[0x07]	401119	1		T1	68		T3	682		T4	142
valid_sources[0x08]	401194	1		T1	92		T3	737		T4	117
valid_sources[0x09]	1107957	1		T1	64		T3	715		T4	117
valid_sources[0x0a]	403888	1		T1	102		T3	672		T4	141
valid_sources[0x0b]	997956	1		T1	44		T3	774		T4	113
valid_sources[0x0c]	401217	1		T1	68		T3	803		T4	171
valid_sources[0x0d]	829636	1		T1	96		T3	804		T4	162
valid_sources[0x0e]	403218	1		T1	88		T3	743		T4	135
valid_sources[0x0f]	402998	1		T1	58		T3	699		T4	168
valid_sources[0x10]	401896	1		T1	89		T3	723		T4	137
valid_sources[0x11]	639197	1		T1	126		T3	708		T4	161
valid_sources[0x12]	400702	1		T1	77		T3	766		T4	110
valid_sources[0x13]	2552169	1		T1	63		T3	737		T4	125
valid_sources[0x14]	404170	1		T1	54		T3	744		T4	139
valid_sources[0x15]	403094	1		T1	92		T3	760		T4	137
valid_sources[0x16]	415349	1		T1	75		T3	764		T4	164
valid_sources[0x17]	403016	1		T1	55		T3	743		T4	152
valid_sources[0x18]	1056920	1		T1	88		T3	728		T4	163
valid_sources[0x19]	516321	1		T1	109		T3	769		T4	157
valid_sources[0x1a]	402214	1		T1	35		T3	696		T4	167
valid_sources[0x1b]	406747	1		T1	73		T3	711		T4	186
valid_sources[0x1c]	402329	1		T1	77		T3	742		T4	146
valid_sources[0x1d]	404012	1		T1	84		T3	729		T4	158
valid_sources[0x1e]	401119	1		T1	86		T3	766		T4	176
valid_sources[0x1f]	401615	1		T1	65		T3	789		T4	165
valid_sources[0x20]	399910	1		T1	94		T3	667		T4	125
valid_sources[0x21]	401308	1		T1	74		T3	754		T4	161
valid_sources[0x22]	868638	1		T1	74		T3	760		T4	170
valid_sources[0x23]	401593	1		T1	117		T3	728		T4	188
valid_sources[0x24]	398256	1		T1	69		T3	715		T4	122
valid_sources[0x25]	400989	1		T1	93		T3	751		T4	158
valid_sources[0x26]	401881	1		T1	98		T3	773		T4	141
valid_sources[0x27]	398455	1		T1	73		T3	691		T4	102
valid_sources[0x28]	401459	1		T1	70		T3	765		T4	136
valid_sources[0x29]	763993	1		T1	60		T3	733		T4	137
valid_sources[0x2a]	400956	1		T1	99		T3	758		T4	134
valid_sources[0x2b]	400926	1		T1	81		T3	703		T4	165
valid_sources[0x2c]	397706	1		T1	126		T3	739		T4	141
valid_sources[0x2d]	762530	1		T1	87		T3	727		T4	177
valid_sources[0x2e]	403136	1		T1	84		T3	742		T4	106
valid_sources[0x2f]	403724	1		T1	84		T3	795		T4	116
valid_sources[0x30]	556066	1		T1	62		T3	694		T4	114
valid_sources[0x31]	405301	1		T1	102		T3	712		T4	176
valid_sources[0x32]	398390	1		T1	78		T3	717		T4	143
valid_sources[0x33]	1771758	1		T1	116		T3	734		T4	180
valid_sources[0x34]	402193	1		T1	86		T3	789		T4	134
valid_sources[0x35]	398982	1		T1	88		T3	780		T4	189
valid_sources[0x36]	399933	1		T1	113		T3	702		T4	185
valid_sources[0x37]	403001	1		T1	96		T3	755		T4	145
valid_sources[0x38]	429809	1		T1	73		T3	754		T4	156
valid_sources[0x39]	471431	1		T1	63		T3	750		T4	138
valid_sources[0x3a]	418493	1		T1	71		T3	726		T4	122
valid_sources[0x3b]	2405684	1		T1	87		T3	733		T4	157
valid_sources[0x3c]	402556	1		T1	92		T3	685		T4	175
valid_sources[0x3d]	558866	1		T1	123		T3	738		T4	196
valid_sources[0x3e]	400876	1		T1	98		T3	737		T4	125
valid_sources[0x3f]	997320	1		T1	57		T3	725		T4	147
valid_sources[0x40]	403501	1		T1	67		T3	714		T4	143
valid_sources[0x41]	402397	1		T1	54		T3	781		T4	114
valid_sources[0x42]	402988	1		T1	103		T3	721		T4	140
valid_sources[0x43]	402119	1		T1	74		T3	742		T4	142
valid_sources[0x44]	457828	1		T1	89		T3	662		T4	143
valid_sources[0x45]	415458	1		T1	118		T3	767		T4	171
valid_sources[0x46]	403852	1		T1	79		T3	670		T4	179
valid_sources[0x47]	398722	1		T1	77		T3	669		T4	145
valid_sources[0x48]	400577	1		T1	79		T3	735		T4	146
valid_sources[0x49]	399442	1		T1	40		T3	718		T4	143
valid_sources[0x4a]	404407	1		T1	47		T3	746		T4	144
valid_sources[0x4b]	403689	1		T1	75		T3	779		T4	138
valid_sources[0x4c]	397997	1		T1	111		T3	711		T4	149
valid_sources[0x4d]	447676	1		T1	83		T3	791		T4	129
valid_sources[0x4e]	403347	1		T1	42		T3	729		T4	122
valid_sources[0x4f]	818113	1		T1	57		T3	743		T4	157
valid_sources[0x50]	708627	1		T1	79		T3	652		T4	169
valid_sources[0x51]	401257	1		T1	71		T3	729		T4	149
valid_sources[0x52]	400542	1		T1	80		T3	749		T4	161
valid_sources[0x53]	403321	1		T1	96		T3	678		T4	160
valid_sources[0x54]	400251	1		T1	81		T3	740		T4	209
valid_sources[0x55]	518114	1		T1	100		T3	731		T4	134
valid_sources[0x56]	401003	1		T1	92		T3	735		T4	126
valid_sources[0x57]	402276	1		T1	59		T3	790		T4	140
valid_sources[0x58]	848965	1		T1	90		T3	698		T4	165
valid_sources[0x59]	401604	1		T1	73		T3	648		T4	153
valid_sources[0x5a]	4584857	1		T1	86		T3	746		T4	193
valid_sources[0x5b]	404211	1		T1	86		T3	694		T4	133
valid_sources[0x5c]	400505	1		T1	66		T3	805		T4	169
valid_sources[0x5d]	402532	1		T1	58		T3	774		T4	158
valid_sources[0x5e]	437056	1		T1	52		T3	725		T4	198
valid_sources[0x5f]	402013	1		T1	57		T3	730		T4	206
valid_sources[0x60]	403370	1		T1	95		T3	678		T4	154
valid_sources[0x61]	402392	1		T1	42		T3	794		T4	118
valid_sources[0x62]	400825	1		T1	46		T3	751		T4	144
valid_sources[0x63]	402180	1		T1	113		T3	713		T4	180
valid_sources[0x64]	466705	1		T1	81		T3	717		T4	152
valid_sources[0x65]	521866	1		T1	80		T3	761		T4	166
valid_sources[0x66]	401688	1		T1	41		T3	758		T4	167
valid_sources[0x67]	415940	1		T1	86		T3	688		T4	123
valid_sources[0x68]	401181	1		T1	72		T3	731		T4	167
valid_sources[0x69]	400455	1		T1	89		T3	719		T4	148
valid_sources[0x6a]	403842	1		T1	108		T3	760		T4	161
valid_sources[0x6b]	408661	1		T1	76		T3	727		T4	151
valid_sources[0x6c]	403581	1		T1	68		T3	770		T4	159
valid_sources[0x6d]	482462	1		T1	91		T3	688		T4	192
valid_sources[0x6e]	404818	1		T1	96		T3	652		T4	155
valid_sources[0x6f]	404798	1		T1	114		T3	724		T4	170
valid_sources[0x70]	401408	1		T1	94		T3	712		T4	153
valid_sources[0x71]	397389	1		T1	67		T3	762		T4	108
valid_sources[0x72]	404389	1		T1	40		T3	828		T4	181
valid_sources[0x73]	400385	1		T1	53		T3	694		T4	130
valid_sources[0x74]	405493	1		T1	122		T3	681		T4	144
valid_sources[0x75]	404636	1		T1	92		T3	755		T4	142
valid_sources[0x76]	658081	1		T1	75		T3	687		T4	218
valid_sources[0x77]	400085	1		T1	67		T3	731		T4	146
valid_sources[0x78]	403709	1		T1	87		T3	776		T4	162
valid_sources[0x79]	415123	1		T1	47		T3	754		T4	122
valid_sources[0x7a]	407976	1		T1	68		T3	734		T4	184
valid_sources[0x7b]	551984	1		T1	98		T3	752		T4	135
valid_sources[0x7c]	510111	1		T1	89		T3	771		T4	174
valid_sources[0x7d]	403277	1		T1	70		T3	695		T4	131
valid_sources[0x7e]	411682	1		T1	81		T3	749		T4	124
valid_sources[0x7f]	403555	1		T1	61		T3	763		T4	123
valid_sources[0x80]	403460	1		T1	103		T3	767		T4	138

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68396060

1

T1

10117

T2

17218

T3

93731

values[0x0]

all_enables

biggest_size

659318

1

T1

38

T2

18

T3

13

values[0x1]

all_enables

biggest_size

656242

1

T1

19

T2

26

T3

13