Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2256379	0	0
cfg0_rd_A	2147483647	10092	0	0
compare_lower0_0_rd_A	2147483647	10567	0	0
compare_upper0_0_rd_A	2147483647	9652	0	0
ctrl_rd_A	2147483647	9527	0	0
intr_enable0_rd_A	2147483647	11907	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2256379	0	0
T13	670844	19759	0	0
T14	0	153327	0	0
T15	0	128059	0	0
T37	0	165750	0	0
T38	0	247229	0	0
T39	0	206698	0	0
T40	0	67567	0	0
T41	0	283617	0	0
T42	0	124632	0	0
T43	0	219242	0	0
T44	867104	0	0	0
T45	377036	0	0	0
T46	113225	0	0	0
T47	9911	0	0	0
T48	124301	0	0	0
T49	977875	0	0	0
T50	761049	0	0	0
T51	600354	0	0	0
T52	475377	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10092	0	0
T13	670844	146	0	0
T31	0	118	0	0
T37	0	1745	0	0
T39	0	2225	0	0
T41	0	2779	0	0
T42	0	1237	0	0
T44	867104	0	0	0
T45	377036	0	0	0
T46	113225	0	0	0
T47	9911	0	0	0
T48	124301	0	0	0
T49	977875	0	0	0
T50	761049	0	0	0
T51	600354	0	0	0
T52	475377	0	0	0
T53	0	1106	0	0
T54	0	6	0	0
T55	0	22	0	0
T56	0	6	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10567	0	0
T13	670844	132	0	0
T31	0	85	0	0
T37	0	1890	0	0
T39	0	2093	0	0
T41	0	3208	0	0
T42	0	1404	0	0
T44	867104	0	0	0
T45	377036	0	0	0
T46	113225	0	0	0
T47	9911	0	0	0
T48	124301	0	0	0
T49	977875	0	0	0
T50	761049	0	0	0
T51	600354	0	0	0
T52	475377	0	0	0
T53	0	1101	0	0
T54	0	2	0	0
T55	0	17	0	0
T57	0	2	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9652	0	0
T13	670844	109	0	0
T31	0	66	0	0
T37	0	1594	0	0
T39	0	2062	0	0
T41	0	2815	0	0
T42	0	1373	0	0
T44	867104	0	0	0
T45	377036	0	0	0
T46	113225	0	0	0
T47	9911	0	0	0
T48	124301	0	0	0
T49	977875	0	0	0
T50	761049	0	0	0
T51	600354	0	0	0
T52	475377	0	0	0
T53	0	1108	0	0
T54	0	2	0	0
T55	0	19	0	0
T56	0	18	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9527	0	0
T13	670844	107	0	0
T31	0	68	0	0
T37	0	1634	0	0
T39	0	2061	0	0
T41	0	2813	0	0
T42	0	1240	0	0
T44	867104	0	0	0
T45	377036	0	0	0
T46	113225	0	0	0
T47	9911	0	0	0
T48	124301	0	0	0
T49	977875	0	0	0
T50	761049	0	0	0
T51	600354	0	0	0
T52	475377	0	0	0
T53	0	1081	0	0
T54	0	6	0	0
T55	0	25	0	0
T56	0	18	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11907	0	0
T13	670844	125	0	0
T37	0	1891	0	0
T39	0	2135	0	0
T44	867104	0	0	0
T45	377036	0	0	0
T46	113225	0	0	0
T47	9911	0	0	0
T48	124301	0	0	0
T49	977875	0	0	0
T50	761049	0	0	0
T51	600354	0	0	0
T52	475377	9	0	0
T58	0	84	0	0
T59	0	36	0	0
T60	0	42	0	0
T61	0	80	0	0
T62	0	69	0	0
T63	0	18	0	0