Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59852116	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	61103435	1		T1	171945		T2	153		T3	207625

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	119878485	1		T1	343200		T2	312		T3	414882
values[0x0]	513205	1		T1	9		T2	13		T3	27
values[0x1]	563861	1		T1	10		T2	8		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47804618	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	73150933	1		T1	206381		T2	188		T3	249485

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	324734	1		T1	1256		T3	1719		T4	19
valid_sources[0x01]	320104	1		T1	1561		T3	1593		T4	23
valid_sources[0x02]	395066	1		T1	1210		T3	1668		T4	16
valid_sources[0x03]	324136	1		T1	1473		T3	1627		T4	21
valid_sources[0x04]	821970	1		T1	1214		T3	1518		T4	23
valid_sources[0x05]	356539	1		T1	1460		T3	1682		T4	20
valid_sources[0x06]	323340	1		T1	1425		T2	2		T3	1483
valid_sources[0x07]	325028	1		T1	1280		T3	1461		T4	14
valid_sources[0x08]	323802	1		T1	1209		T2	1		T3	1698
valid_sources[0x09]	322448	1		T1	1306		T3	1455		T4	25
valid_sources[0x0a]	320081	1		T1	1290		T3	1999		T4	21
valid_sources[0x0b]	320544	1		T1	1482		T2	5		T3	1706
valid_sources[0x0c]	322677	1		T1	1483		T3	1628		T4	24
valid_sources[0x0d]	322589	1		T1	1338		T3	1604		T4	9
valid_sources[0x0e]	758275	1		T1	1375		T3	1827		T4	11
valid_sources[0x0f]	370202	1		T1	1259		T2	2		T3	1589
valid_sources[0x10]	319177	1		T1	1252		T3	1691		T4	14
valid_sources[0x11]	486498	1		T1	1250		T2	2		T3	1583
valid_sources[0x12]	322237	1		T1	1484		T3	1596		T4	19
valid_sources[0x13]	1036842	1		T1	1433		T3	1785		T4	19
valid_sources[0x14]	325016	1		T1	1527		T3	1414		T4	17
valid_sources[0x15]	328444	1		T1	1259		T3	1449		T4	17
valid_sources[0x16]	322466	1		T1	1151		T3	1552		T4	18
valid_sources[0x17]	325092	1		T1	1364		T3	1376		T4	13
valid_sources[0x18]	820299	1		T1	1408		T2	3		T3	1699
valid_sources[0x19]	324270	1		T1	1525		T3	1874		T4	7
valid_sources[0x1a]	324564	1		T1	1112		T2	2		T3	1617
valid_sources[0x1b]	324220	1		T1	1254		T2	2		T3	1603
valid_sources[0x1c]	321119	1		T1	1207		T3	1802		T4	23
valid_sources[0x1d]	323353	1		T1	1419		T3	1646		T4	8
valid_sources[0x1e]	322172	1		T1	1393		T3	1336		T4	19
valid_sources[0x1f]	337340	1		T1	1129		T2	1		T3	1521
valid_sources[0x20]	323106	1		T1	1311		T2	2		T3	1833
valid_sources[0x21]	648775	1		T1	1354		T3	1679		T4	20
valid_sources[0x22]	324041	1		T1	1118		T3	1648		T4	22
valid_sources[0x23]	322008	1		T1	1209		T2	12		T3	1498
valid_sources[0x24]	325473	1		T1	1319		T3	1617		T4	18
valid_sources[0x25]	327382	1		T1	1552		T2	7		T3	1545
valid_sources[0x26]	321818	1		T1	1603		T2	6		T3	1421
valid_sources[0x27]	319214	1		T1	1263		T3	1671		T4	25
valid_sources[0x28]	324869	1		T1	1266		T3	1597		T4	12
valid_sources[0x29]	335003	1		T1	1405		T3	1469		T4	11
valid_sources[0x2a]	321321	1		T1	1503		T2	2		T3	1380
valid_sources[0x2b]	322726	1		T1	1456		T2	2		T3	1897
valid_sources[0x2c]	322252	1		T1	1374		T2	6		T3	1297
valid_sources[0x2d]	324181	1		T1	1388		T3	1590		T4	22
valid_sources[0x2e]	324028	1		T1	1495		T3	1830		T4	17
valid_sources[0x2f]	323399	1		T1	1256		T2	2		T3	1401
valid_sources[0x30]	345353	1		T1	1500		T3	1602		T4	8
valid_sources[0x31]	595842	1		T1	1442		T3	1543		T4	12
valid_sources[0x32]	741034	1		T1	1261		T3	1758		T4	18
valid_sources[0x33]	323352	1		T1	1433		T2	2		T3	1402
valid_sources[0x34]	323707	1		T1	1446		T2	7		T3	1667
valid_sources[0x35]	322102	1		T1	1448		T3	1628		T4	13
valid_sources[0x36]	322005	1		T1	1436		T3	1825		T4	17
valid_sources[0x37]	323671	1		T1	1364		T3	1473		T4	19
valid_sources[0x38]	326044	1		T1	1316		T3	1525		T4	18
valid_sources[0x39]	322293	1		T1	1330		T3	1668		T4	15
valid_sources[0x3a]	324743	1		T1	1242		T3	1537		T4	19
valid_sources[0x3b]	322307	1		T1	1386		T3	1724		T4	16
valid_sources[0x3c]	959627	1		T1	1452		T3	1847		T4	25
valid_sources[0x3d]	320644	1		T1	1215		T3	1726		T4	12
valid_sources[0x3e]	324316	1		T1	1348		T2	1		T3	1608
valid_sources[0x3f]	319159	1		T1	1306		T3	1494		T4	23
valid_sources[0x40]	320652	1		T1	1300		T3	1558		T4	16
valid_sources[0x41]	354752	1		T1	1431		T3	1600		T4	27
valid_sources[0x42]	320904	1		T1	1360		T3	1879		T4	17
valid_sources[0x43]	321206	1		T1	1291		T3	1648		T4	23
valid_sources[0x44]	326031	1		T1	1565		T3	1566		T4	20
valid_sources[0x45]	767022	1		T1	1268		T3	1526		T4	21
valid_sources[0x46]	330905	1		T1	1413		T3	1522		T4	13
valid_sources[0x47]	321038	1		T1	1416		T2	1		T3	1750
valid_sources[0x48]	320354	1		T1	1359		T3	1691		T4	19
valid_sources[0x49]	322978	1		T1	1246		T2	4		T3	1659
valid_sources[0x4a]	2952090	1		T1	1332		T3	1764		T4	26
valid_sources[0x4b]	322470	1		T1	1276		T2	10		T3	1401
valid_sources[0x4c]	360322	1		T1	1144		T2	2		T3	1658
valid_sources[0x4d]	324428	1		T1	1320		T2	2		T3	1600
valid_sources[0x4e]	323883	1		T1	1253		T3	1787		T4	10
valid_sources[0x4f]	322090	1		T1	1176		T3	1405		T4	29
valid_sources[0x50]	324361	1		T1	1392		T3	1434		T4	22
valid_sources[0x51]	2892230	1		T1	1283		T2	5		T3	1720
valid_sources[0x52]	325400	1		T1	1437		T3	1473		T4	27
valid_sources[0x53]	320581	1		T1	1345		T2	9		T3	1778
valid_sources[0x54]	326318	1		T1	1496		T3	1874		T4	18
valid_sources[0x55]	1251325	1		T1	1211		T2	8		T3	1557
valid_sources[0x56]	326204	1		T1	1207		T2	1		T3	1770
valid_sources[0x57]	323545	1		T1	1362		T3	1431		T4	15
valid_sources[0x58]	856092	1		T1	1352		T2	4		T3	1532
valid_sources[0x59]	320931	1		T1	1269		T3	1327		T4	24
valid_sources[0x5a]	837371	1		T1	1388		T3	1621		T4	16
valid_sources[0x5b]	653919	1		T1	1433		T3	1769		T4	15
valid_sources[0x5c]	325256	1		T1	1386		T2	1		T3	1619
valid_sources[0x5d]	321612	1		T1	1429		T3	1625		T4	35
valid_sources[0x5e]	494618	1		T1	1380		T3	1644		T4	17
valid_sources[0x5f]	2683390	1		T1	1384		T3	1464		T4	14
valid_sources[0x60]	324284	1		T1	1306		T3	1601		T4	12
valid_sources[0x61]	319800	1		T1	1290		T3	1547		T4	9
valid_sources[0x62]	414715	1		T1	1269		T2	4		T3	1627
valid_sources[0x63]	324415	1		T1	1325		T3	1616		T4	15
valid_sources[0x64]	322000	1		T1	1357		T3	1763		T4	19
valid_sources[0x65]	323538	1		T1	1308		T3	1899		T4	19
valid_sources[0x66]	340261	1		T1	1253		T3	1492		T4	13
valid_sources[0x67]	322589	1		T1	1509		T3	1614		T4	34
valid_sources[0x68]	321698	1		T1	1180		T2	6		T3	1543
valid_sources[0x69]	2138966	1		T1	1303		T3	1440		T4	23
valid_sources[0x6a]	322744	1		T1	1248		T3	1680		T4	20
valid_sources[0x6b]	623959	1		T1	1459		T2	2		T3	1568
valid_sources[0x6c]	323662	1		T1	1424		T2	1		T3	1507
valid_sources[0x6d]	321783	1		T1	1419		T2	8		T3	1655
valid_sources[0x6e]	321980	1		T1	1241		T2	2		T3	1754
valid_sources[0x6f]	325678	1		T1	1177		T2	3		T3	1633
valid_sources[0x70]	322374	1		T1	1307		T3	1554		T4	18
valid_sources[0x71]	320500	1		T1	1361		T2	9		T3	1604
valid_sources[0x72]	573126	1		T1	1291		T2	2		T3	1504
valid_sources[0x73]	410504	1		T1	1444		T3	1703		T4	19
valid_sources[0x74]	322287	1		T1	1224		T2	1		T3	1637
valid_sources[0x75]	322731	1		T1	1275		T3	1779		T4	19
valid_sources[0x76]	322436	1		T1	1205		T2	3		T3	1697
valid_sources[0x77]	325363	1		T1	1347		T3	1589		T4	23
valid_sources[0x78]	321775	1		T1	1318		T3	1593		T4	22
valid_sources[0x79]	324011	1		T1	1306		T3	1617		T4	19
valid_sources[0x7a]	322099	1		T1	1275		T3	1724		T4	19
valid_sources[0x7b]	572073	1		T1	1302		T2	20		T3	1621
valid_sources[0x7c]	323153	1		T1	1330		T3	1548		T4	9
valid_sources[0x7d]	321682	1		T1	1470		T3	1245		T4	24
valid_sources[0x7e]	1197266	1		T1	1386		T3	1607		T4	17
valid_sources[0x7f]	322454	1		T1	1481		T3	1471		T4	16
valid_sources[0x80]	408892	1		T1	1283		T2	3		T3	1576

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60100297

1

T1

171932

T2

139

T3

207580

values[0x0]

all_enables

biggest_size

503102

1

T1

7

T2

9

T3

24

values[0x1]

all_enables

biggest_size

500036

1

T1

6

T2

5

T3

21