Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1725276	0	0
cfg0_rd_A	2147483647	6633	0	0
compare_lower0_0_rd_A	2147483647	7238	0	0
compare_upper0_0_rd_A	2147483647	6485	0	0
ctrl_rd_A	2147483647	6089	0	0
intr_enable0_rd_A	2147483647	8900	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1725276	0	0
T12	290025	78163	0	0
T13	470103	66349	0	0
T14	0	245602	0	0
T31	0	103138	0	0
T32	0	47704	0	0
T33	0	22331	0	0
T34	0	164944	0	0
T35	0	160410	0	0
T36	0	23746	0	0
T37	0	177674	0	0
T38	109479	0	0	0
T39	871419	0	0	0
T40	263194	0	0	0
T41	538147	0	0	0
T42	189920	0	0	0
T43	985959	0	0	0
T44	752478	0	0	0
T45	476831	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6633	0	0
T12	290025	358	0	0
T13	470103	0	0	0
T14	0	2341	0	0
T27	0	97	0	0
T38	109479	0	0	0
T39	871419	0	0	0
T40	263194	0	0	0
T41	538147	0	0	0
T42	189920	0	0	0
T43	985959	0	0	0
T44	752478	0	0	0
T45	476831	0	0	0
T46	0	629	0	0
T47	0	438	0	0
T48	0	1086	0	0
T49	0	699	0	0
T50	0	49	0	0
T51	0	4	0	0
T52	0	8	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7238	0	0
T12	290025	607	0	0
T13	470103	0	0	0
T14	0	2678	0	0
T27	0	57	0	0
T38	109479	0	0	0
T39	871419	0	0	0
T40	263194	0	0	0
T41	538147	0	0	0
T42	189920	0	0	0
T43	985959	0	0	0
T44	752478	0	0	0
T45	476831	0	0	0
T46	0	534	0	0
T47	0	628	0	0
T48	0	1156	0	0
T49	0	717	0	0
T50	0	42	0	0
T51	0	3	0	0
T52	0	5	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6485	0	0
T12	290025	443	0	0
T13	470103	0	0	0
T14	0	2396	0	0
T27	0	89	0	0
T38	109479	0	0	0
T39	871419	0	0	0
T40	263194	0	0	0
T41	538147	0	0	0
T42	189920	0	0	0
T43	985959	0	0	0
T44	752478	0	0	0
T45	476831	0	0	0
T46	0	453	0	0
T47	0	570	0	0
T48	0	1088	0	0
T49	0	663	0	0
T50	0	17	0	0
T51	0	9	0	0
T52	0	7	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6089	0	0
T12	290025	385	0	0
T13	470103	0	0	0
T14	0	2321	0	0
T27	0	55	0	0
T38	109479	0	0	0
T39	871419	0	0	0
T40	263194	0	0	0
T41	538147	0	0	0
T42	189920	0	0	0
T43	985959	0	0	0
T44	752478	0	0	0
T45	476831	0	0	0
T46	0	490	0	0
T47	0	388	0	0
T48	0	977	0	0
T49	0	627	0	0
T50	0	17	0	0
T51	0	12	0	0
T52	0	14	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8900	0	0
T7	197401	30	0	0
T8	258946	0	0	0
T9	3558	0	0	0
T10	395498	0	0	0
T11	469167	0	0	0
T12	0	590	0	0
T14	0	2909	0	0
T19	2120	0	0	0
T20	132465	0	0	0
T21	113201	0	0	0
T22	108204	0	0	0
T23	934332	0	0	0
T30	0	56	0	0
T46	0	659	0	0
T53	0	29	0	0
T54	0	14	0	0
T55	0	106	0	0
T56	0	10	0	0
T57	0	82	0	0