Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2565827	0	0
cfg0_rd_A	2147483647	7166	0	0
compare_lower0_0_rd_A	2147483647	7813	0	0
compare_upper0_0_rd_A	2147483647	6863	0	0
ctrl_rd_A	2147483647	6640	0	0
intr_enable0_rd_A	2147483647	8770	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2565827	0	0
T11	622392	118238	0	0
T12	240087	60969	0	0
T13	0	389626	0	0
T35	0	105778	0	0
T36	0	172010	0	0
T37	0	307677	0	0
T38	0	211386	0	0
T39	0	58498	0	0
T40	0	75614	0	0
T41	0	132494	0	0
T42	669093	0	0	0
T43	390535	0	0	0
T44	140950	0	0	0
T45	927474	0	0	0
T46	171744	0	0	0
T47	383630	0	0	0
T48	253067	0	0	0
T49	413367	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7166	0	0
T12	240087	596	0	0
T28	0	76	0	0
T29	0	46	0	0
T36	0	1758	0	0
T39	0	671	0	0
T40	0	373	0	0
T44	140950	0	0	0
T45	927474	0	0	0
T46	171744	0	0	0
T47	383630	0	0	0
T48	253067	0	0	0
T49	413367	0	0	0
T50	0	979	0	0
T51	0	342	0	0
T52	0	35	0	0
T53	0	4	0	0
T54	431581	0	0	0
T55	374871	0	0	0
T56	743596	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7813	0	0
T12	240087	717	0	0
T28	0	65	0	0
T29	0	13	0	0
T36	0	1933	0	0
T39	0	684	0	0
T40	0	524	0	0
T44	140950	0	0	0
T45	927474	0	0	0
T46	171744	0	0	0
T47	383630	0	0	0
T48	253067	0	0	0
T49	413367	0	0	0
T50	0	1152	0	0
T51	0	407	0	0
T52	0	33	0	0
T53	0	9	0	0
T54	431581	0	0	0
T55	374871	0	0	0
T56	743596	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6863	0	0
T12	240087	560	0	0
T28	0	26	0	0
T29	0	22	0	0
T36	0	1979	0	0
T39	0	604	0	0
T40	0	373	0	0
T44	140950	0	0	0
T45	927474	0	0	0
T46	171744	0	0	0
T47	383630	0	0	0
T48	253067	0	0	0
T49	413367	0	0	0
T50	0	843	0	0
T51	0	345	0	0
T52	0	12	0	0
T53	0	8	0	0
T54	431581	0	0	0
T55	374871	0	0	0
T56	743596	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6640	0	0
T12	240087	621	0	0
T28	0	45	0	0
T29	0	39	0	0
T36	0	1626	0	0
T39	0	705	0	0
T40	0	322	0	0
T44	140950	0	0	0
T45	927474	0	0	0
T46	171744	0	0	0
T47	383630	0	0	0
T48	253067	0	0	0
T49	413367	0	0	0
T50	0	884	0	0
T51	0	249	0	0
T52	0	24	0	0
T53	0	7	0	0
T54	431581	0	0	0
T55	374871	0	0	0
T56	743596	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8770	0	0
T9	165827	10	0	0
T10	277444	0	0	0
T12	0	812	0	0
T34	501647	0	0	0
T36	0	2059	0	0
T39	0	771	0	0
T40	0	509	0	0
T57	0	64	0	0
T58	0	56	0	0
T59	0	46	0	0
T60	0	41	0	0
T61	0	17	0	0
T62	354435	0	0	0
T63	116227	0	0	0
T64	396644	0	0	0
T65	663073	0	0	0
T66	855820	0	0	0
T67	111399	0	0	0
T68	141606	0	0	0