Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58445917	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	60743416	1		T1	17154		T2	53725		T3	5365

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	117214781	1		T1	34088		T2	106672		T3	10852
values[0x0]	938093	1		T1	13		T2	30		T3	8
values[0x1]	1036459	1		T1	20		T2	22		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46654230	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	72535103	1		T1	20528		T2	64404		T3	6456

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	353263	1		T1	122		T2	298		T3	37
valid_sources[0x01]	349864	1		T1	135		T2	427		T3	87
valid_sources[0x02]	354538	1		T1	173		T2	520		T3	32
valid_sources[0x03]	353978	1		T1	135		T2	424		T3	28
valid_sources[0x04]	520545	1		T1	154		T2	337		T3	33
valid_sources[0x05]	807449	1		T1	149		T2	330		T3	38
valid_sources[0x06]	358739	1		T1	150		T2	492		T3	56
valid_sources[0x07]	354322	1		T1	128		T2	420		T3	78
valid_sources[0x08]	353775	1		T1	135		T2	425		T3	49
valid_sources[0x09]	353097	1		T1	139		T2	445		T3	24
valid_sources[0x0a]	350192	1		T1	123		T2	346		T3	32
valid_sources[0x0b]	1037414	1		T1	111		T2	354		T3	44
valid_sources[0x0c]	352289	1		T1	147		T2	404		T3	57
valid_sources[0x0d]	352581	1		T1	129		T2	378		T3	16
valid_sources[0x0e]	351496	1		T1	117		T2	472		T3	41
valid_sources[0x0f]	348231	1		T1	155		T2	404		T3	85
valid_sources[0x10]	350614	1		T1	125		T2	331		T3	50
valid_sources[0x11]	649375	1		T1	128		T2	489		T3	31
valid_sources[0x12]	350872	1		T1	127		T2	351		T3	41
valid_sources[0x13]	568599	1		T1	127		T2	449		T3	60
valid_sources[0x14]	351644	1		T1	129		T2	368		T3	55
valid_sources[0x15]	352351	1		T1	127		T2	386		T3	64
valid_sources[0x16]	348541	1		T1	143		T2	419		T3	17
valid_sources[0x17]	366958	1		T1	142		T2	382		T3	58
valid_sources[0x18]	350040	1		T1	145		T2	361		T3	88
valid_sources[0x19]	352232	1		T1	123		T2	416		T3	27
valid_sources[0x1a]	771261	1		T1	125		T2	353		T3	65
valid_sources[0x1b]	353014	1		T1	114		T2	503		T3	57
valid_sources[0x1c]	351744	1		T1	140		T2	306		T3	39
valid_sources[0x1d]	354139	1		T1	115		T2	528		T3	62
valid_sources[0x1e]	1092471	1		T1	137		T2	489		T3	26
valid_sources[0x1f]	352006	1		T1	138		T2	505		T3	22
valid_sources[0x20]	352238	1		T1	145		T2	417		T3	57
valid_sources[0x21]	383858	1		T1	123		T2	486		T3	26
valid_sources[0x22]	354298	1		T1	150		T2	468		T3	19
valid_sources[0x23]	646783	1		T1	132		T2	363		T3	32
valid_sources[0x24]	354380	1		T1	133		T2	449		T3	59
valid_sources[0x25]	352710	1		T1	136		T2	403		T3	21
valid_sources[0x26]	354344	1		T1	116		T2	399		T3	22
valid_sources[0x27]	544337	1		T1	145		T2	408		T3	54
valid_sources[0x28]	354438	1		T1	157		T2	406		T3	27
valid_sources[0x29]	352247	1		T1	168		T2	441		T3	26
valid_sources[0x2a]	350151	1		T1	149		T2	321		T3	41
valid_sources[0x2b]	758892	1		T1	125		T2	389		T3	71
valid_sources[0x2c]	350374	1		T1	151		T2	413		T3	54
valid_sources[0x2d]	351585	1		T1	132		T2	451		T3	45
valid_sources[0x2e]	352369	1		T1	130		T2	463		T3	21
valid_sources[0x2f]	348588	1		T1	134		T2	398		T3	39
valid_sources[0x30]	350006	1		T1	128		T2	398		T3	53
valid_sources[0x31]	355443	1		T1	118		T2	516		T3	90
valid_sources[0x32]	787644	1		T1	145		T2	435		T3	35
valid_sources[0x33]	353434	1		T1	122		T2	362		T3	62
valid_sources[0x34]	354735	1		T1	151		T2	479		T3	62
valid_sources[0x35]	643019	1		T1	143		T2	486		T3	19
valid_sources[0x36]	353469	1		T1	143		T2	383		T3	50
valid_sources[0x37]	352264	1		T1	140		T2	561		T3	13
valid_sources[0x38]	354542	1		T1	118		T2	382		T3	48
valid_sources[0x39]	912547	1		T1	129		T2	369		T3	28
valid_sources[0x3a]	352806	1		T1	137		T2	386		T3	46
valid_sources[0x3b]	352494	1		T1	146		T2	448		T3	46
valid_sources[0x3c]	351883	1		T1	121		T2	353		T3	58
valid_sources[0x3d]	354607	1		T1	131		T2	494		T3	28
valid_sources[0x3e]	1058330	1		T1	130		T2	463		T3	56
valid_sources[0x3f]	354947	1		T1	109		T2	345		T3	12
valid_sources[0x40]	352221	1		T1	151		T2	369		T3	30
valid_sources[0x41]	694302	1		T1	128		T2	433		T3	46
valid_sources[0x42]	677965	1		T1	107		T2	456		T3	31
valid_sources[0x43]	350568	1		T1	142		T2	367		T3	71
valid_sources[0x44]	347863	1		T1	107		T2	413		T3	16
valid_sources[0x45]	352576	1		T1	155		T2	333		T3	15
valid_sources[0x46]	365109	1		T1	126		T2	411		T3	29
valid_sources[0x47]	348818	1		T1	102		T2	388		T3	58
valid_sources[0x48]	811879	1		T1	140		T2	286		T3	58
valid_sources[0x49]	1331023	1		T1	128		T2	344		T3	44
valid_sources[0x4a]	352551	1		T1	146		T2	373		T3	66
valid_sources[0x4b]	351497	1		T1	136		T2	424		T3	83
valid_sources[0x4c]	352367	1		T1	130		T2	428		T3	67
valid_sources[0x4d]	421573	1		T1	129		T2	512		T3	73
valid_sources[0x4e]	352158	1		T1	135		T2	421		T3	43
valid_sources[0x4f]	353127	1		T1	112		T2	463		T3	31
valid_sources[0x50]	350582	1		T1	126		T2	391		T3	21
valid_sources[0x51]	3794762	1		T1	112		T2	394		T3	32
valid_sources[0x52]	350643	1		T1	136		T2	322		T3	17
valid_sources[0x53]	351052	1		T1	153		T2	358		T3	15
valid_sources[0x54]	352989	1		T1	151		T2	405		T3	3
valid_sources[0x55]	356859	1		T1	129		T2	403		T3	62
valid_sources[0x56]	353353	1		T1	126		T2	424		T3	44
valid_sources[0x57]	355614	1		T1	132		T2	478		T3	50
valid_sources[0x58]	1050738	1		T1	144		T2	479		T3	52
valid_sources[0x59]	349499	1		T1	149		T2	334		T3	37
valid_sources[0x5a]	352558	1		T1	116		T2	362		T3	55
valid_sources[0x5b]	352899	1		T1	150		T2	407		T3	41
valid_sources[0x5c]	358921	1		T1	137		T2	468		T3	41
valid_sources[0x5d]	351451	1		T1	147		T2	486		T3	55
valid_sources[0x5e]	353567	1		T1	144		T2	446		T3	43
valid_sources[0x5f]	354212	1		T1	113		T2	432		T3	35
valid_sources[0x60]	368583	1		T1	156		T2	433		T3	35
valid_sources[0x61]	353803	1		T1	130		T2	417		T3	45
valid_sources[0x62]	351792	1		T1	126		T2	465		T3	42
valid_sources[0x63]	353635	1		T1	157		T2	443		T3	62
valid_sources[0x64]	351815	1		T1	142		T2	376		T3	58
valid_sources[0x65]	353214	1		T1	124		T2	412		T3	54
valid_sources[0x66]	352937	1		T1	132		T2	394		T3	54
valid_sources[0x67]	349655	1		T1	148		T2	413		T3	23
valid_sources[0x68]	351599	1		T1	138		T2	489		T3	59
valid_sources[0x69]	1950802	1		T1	143		T2	317		T3	13
valid_sources[0x6a]	355573	1		T1	132		T2	386		T3	61
valid_sources[0x6b]	372709	1		T1	141		T2	405		T3	73
valid_sources[0x6c]	698178	1		T1	139		T2	490		T3	98
valid_sources[0x6d]	350413	1		T1	127		T2	388		T3	19
valid_sources[0x6e]	557706	1		T1	105		T2	385		T3	24
valid_sources[0x6f]	370718	1		T1	156		T2	451		T3	71
valid_sources[0x70]	1522571	1		T1	136		T2	371		T3	21
valid_sources[0x71]	353263	1		T1	103		T2	450		T3	49
valid_sources[0x72]	354065	1		T1	141		T2	302		T3	27
valid_sources[0x73]	366578	1		T1	129		T2	481		T3	89
valid_sources[0x74]	374574	1		T1	149		T2	349		T3	10
valid_sources[0x75]	352220	1		T1	122		T2	463		T3	24
valid_sources[0x76]	351945	1		T1	120		T2	327		T3	43
valid_sources[0x77]	639106	1		T1	131		T2	480		T3	16
valid_sources[0x78]	348243	1		T1	126		T2	348		T3	9
valid_sources[0x79]	350732	1		T1	123		T2	303		T3	12
valid_sources[0x7a]	381495	1		T1	121		T2	532		T3	32
valid_sources[0x7b]	354566	1		T1	124		T2	450		T3	10
valid_sources[0x7c]	350865	1		T1	115		T2	413		T3	40
valid_sources[0x7d]	353968	1		T1	134		T2	426		T3	52
valid_sources[0x7e]	352833	1		T1	139		T2	565		T3	56
valid_sources[0x7f]	1112571	1		T1	125		T2	389		T3	32
valid_sources[0x80]	1149346	1		T1	137		T2	401		T3	50

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

58899183

1

T1

17129

T2

53688

T3

5354

values[0x0]

all_enables

biggest_size

922675

1

T1

10

T2

24

T3

7

values[0x1]

all_enables

biggest_size

921558

1

T1

15

T2

13

T3

4