Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64546030	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	65857893	1		T1	5956		T2	123504		T3	22588

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	129284334	1		T1	11932		T2	246857		T3	44954
values[0x0]	532027	1		T1	15		T2	19		T3	25
values[0x1]	587562	1		T1	14		T2	21		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51549773	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	78854150	1		T1	7172		T2	148385		T3	27164

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	380304	1		T1	51		T2	870		T3	232
valid_sources[0x01]	1272803	1		T1	37		T2	2079		T3	190
valid_sources[0x02]	381912	1		T1	54		T2	761		T3	208
valid_sources[0x03]	546290	1		T1	39		T2	872		T3	155
valid_sources[0x04]	401078	1		T1	44		T2	162		T3	184
valid_sources[0x05]	379978	1		T1	42		T2	1018		T3	207
valid_sources[0x06]	382232	1		T1	44		T2	921		T3	171
valid_sources[0x07]	381653	1		T1	50		T2	943		T3	204
valid_sources[0x08]	1674837	1		T1	45		T2	1414		T3	153
valid_sources[0x09]	381767	1		T1	43		T2	1249		T3	178
valid_sources[0x0a]	378747	1		T1	53		T2	1132		T3	178
valid_sources[0x0b]	381672	1		T1	46		T2	1174		T3	143
valid_sources[0x0c]	377771	1		T1	51		T2	1020		T3	193
valid_sources[0x0d]	379460	1		T1	51		T2	1572		T3	172
valid_sources[0x0e]	380033	1		T1	40		T2	528		T3	159
valid_sources[0x0f]	375238	1		T1	58		T2	332		T3	177
valid_sources[0x10]	379402	1		T1	43		T2	1005		T3	137
valid_sources[0x11]	381270	1		T1	45		T2	1079		T3	171
valid_sources[0x12]	388604	1		T1	46		T2	481		T3	166
valid_sources[0x13]	502062	1		T1	45		T2	1096		T3	147
valid_sources[0x14]	402594	1		T1	43		T2	767		T3	160
valid_sources[0x15]	421858	1		T1	44		T2	1009		T3	162
valid_sources[0x16]	380024	1		T1	47		T2	518		T3	252
valid_sources[0x17]	379697	1		T1	45		T2	772		T3	153
valid_sources[0x18]	400448	1		T1	46		T2	1439		T3	134
valid_sources[0x19]	401426	1		T1	47		T2	675		T3	154
valid_sources[0x1a]	381632	1		T1	52		T2	703		T3	149
valid_sources[0x1b]	693962	1		T1	40		T2	1728		T3	162
valid_sources[0x1c]	379737	1		T1	51		T2	390		T3	204
valid_sources[0x1d]	390917	1		T1	51		T2	781		T3	169
valid_sources[0x1e]	378401	1		T1	44		T2	852		T3	221
valid_sources[0x1f]	375992	1		T1	30		T2	891		T3	159
valid_sources[0x20]	378139	1		T1	36		T2	634		T3	160
valid_sources[0x21]	378200	1		T1	54		T2	1496		T3	227
valid_sources[0x22]	380611	1		T1	41		T2	1015		T3	203
valid_sources[0x23]	383619	1		T1	56		T2	1486		T3	216
valid_sources[0x24]	2404072	1		T1	48		T2	555		T3	185
valid_sources[0x25]	589138	1		T1	54		T2	625		T3	156
valid_sources[0x26]	375243	1		T1	53		T2	615		T3	159
valid_sources[0x27]	380309	1		T1	54		T2	1716		T3	184
valid_sources[0x28]	379712	1		T1	44		T2	1635		T3	196
valid_sources[0x29]	380878	1		T1	47		T2	855		T3	187
valid_sources[0x2a]	1113161	1		T1	47		T2	1130		T3	193
valid_sources[0x2b]	1205479	1		T1	43		T2	969		T3	185
valid_sources[0x2c]	377979	1		T1	63		T2	791		T3	136
valid_sources[0x2d]	821094	1		T1	53		T2	1374		T3	236
valid_sources[0x2e]	380538	1		T1	47		T2	850		T3	181
valid_sources[0x2f]	379389	1		T1	39		T2	263		T3	140
valid_sources[0x30]	394579	1		T1	42		T2	734		T3	174
valid_sources[0x31]	379663	1		T1	47		T2	1270		T3	181
valid_sources[0x32]	4924239	1		T1	28		T2	376		T3	191
valid_sources[0x33]	401773	1		T1	44		T2	1401		T3	134
valid_sources[0x34]	378054	1		T1	49		T2	542		T3	191
valid_sources[0x35]	381201	1		T1	41		T2	927		T3	167
valid_sources[0x36]	379611	1		T1	44		T2	501		T3	137
valid_sources[0x37]	564948	1		T1	35		T2	1095		T3	187
valid_sources[0x38]	377197	1		T1	54		T2	1095		T3	188
valid_sources[0x39]	382133	1		T1	52		T2	1261		T3	192
valid_sources[0x3a]	425800	1		T1	46		T2	1211		T3	180
valid_sources[0x3b]	948109	1		T1	41		T2	821		T3	145
valid_sources[0x3c]	431372	1		T1	42		T2	453		T3	132
valid_sources[0x3d]	390915	1		T1	42		T2	728		T3	154
valid_sources[0x3e]	389563	1		T1	51		T2	1004		T3	149
valid_sources[0x3f]	646795	1		T1	36		T2	414		T3	168
valid_sources[0x40]	383723	1		T1	45		T2	1088		T3	173
valid_sources[0x41]	372645	1		T1	40		T2	504		T3	194
valid_sources[0x42]	388072	1		T1	44		T2	1237		T3	195
valid_sources[0x43]	1062047	1		T1	50		T2	1102		T3	181
valid_sources[0x44]	381568	1		T1	46		T2	1839		T3	186
valid_sources[0x45]	377877	1		T1	31		T2	852		T3	156
valid_sources[0x46]	379508	1		T1	49		T2	1671		T3	146
valid_sources[0x47]	628991	1		T1	53		T2	684		T3	178
valid_sources[0x48]	378608	1		T1	45		T2	1492		T3	157
valid_sources[0x49]	380738	1		T1	38		T2	994		T3	191
valid_sources[0x4a]	375704	1		T1	45		T2	563		T3	163
valid_sources[0x4b]	390993	1		T1	50		T2	903		T3	163
valid_sources[0x4c]	1680605	1		T1	37		T2	1043		T3	204
valid_sources[0x4d]	387689	1		T1	49		T2	994		T3	127
valid_sources[0x4e]	379826	1		T1	40		T2	1265		T3	146
valid_sources[0x4f]	410859	1		T1	30		T2	1072		T3	168
valid_sources[0x50]	380958	1		T1	56		T2	1118		T3	188
valid_sources[0x51]	463825	1		T1	51		T2	942		T3	194
valid_sources[0x52]	380165	1		T1	47		T2	1415		T3	170
valid_sources[0x53]	380220	1		T1	35		T2	1339		T3	154
valid_sources[0x54]	381788	1		T1	61		T2	1360		T3	202
valid_sources[0x55]	379473	1		T1	39		T2	608		T3	186
valid_sources[0x56]	380643	1		T1	63		T2	1060		T3	199
valid_sources[0x57]	377523	1		T1	53		T2	624		T3	170
valid_sources[0x58]	378474	1		T1	42		T2	780		T3	201
valid_sources[0x59]	1229574	1		T1	46		T2	334		T3	194
valid_sources[0x5a]	400421	1		T1	42		T2	985		T3	132
valid_sources[0x5b]	378573	1		T1	46		T2	929		T3	215
valid_sources[0x5c]	377482	1		T1	48		T2	1670		T3	168
valid_sources[0x5d]	379938	1		T1	41		T2	321		T3	134
valid_sources[0x5e]	381133	1		T1	34		T2	1516		T3	156
valid_sources[0x5f]	380486	1		T1	48		T2	1115		T3	193
valid_sources[0x60]	799461	1		T1	39		T2	1243		T3	180
valid_sources[0x61]	378192	1		T1	47		T2	885		T3	201
valid_sources[0x62]	588645	1		T1	48		T2	1272		T3	191
valid_sources[0x63]	378384	1		T1	53		T2	1406		T3	164
valid_sources[0x64]	378766	1		T1	31		T2	1520		T3	129
valid_sources[0x65]	379029	1		T1	39		T2	663		T3	190
valid_sources[0x66]	376856	1		T1	51		T2	1209		T3	137
valid_sources[0x67]	2018021	1		T1	51		T2	1994		T3	191
valid_sources[0x68]	528475	1		T1	52		T2	768		T3	141
valid_sources[0x69]	375932	1		T1	44		T2	1093		T3	145
valid_sources[0x6a]	380579	1		T1	50		T2	1323		T3	178
valid_sources[0x6b]	378950	1		T1	43		T2	756		T3	184
valid_sources[0x6c]	527513	1		T1	53		T2	1061		T3	191
valid_sources[0x6d]	375738	1		T1	46		T2	1070		T3	205
valid_sources[0x6e]	377714	1		T1	59		T2	1040		T3	139
valid_sources[0x6f]	381979	1		T1	52		T2	468		T3	171
valid_sources[0x70]	551460	1		T1	46		T2	834		T3	227
valid_sources[0x71]	380488	1		T1	47		T2	988		T3	169
valid_sources[0x72]	377315	1		T1	44		T2	1260		T3	192
valid_sources[0x73]	380787	1		T1	55		T2	1319		T3	163
valid_sources[0x74]	396327	1		T1	58		T2	347		T3	167
valid_sources[0x75]	642592	1		T1	55		T2	44		T3	146
valid_sources[0x76]	377238	1		T1	41		T2	1423		T3	178
valid_sources[0x77]	728906	1		T1	48		T2	1569		T3	204
valid_sources[0x78]	382672	1		T1	41		T2	1667		T3	162
valid_sources[0x79]	379834	1		T1	55		T2	940		T3	166
valid_sources[0x7a]	378414	1		T1	53		T2	1378		T3	158
valid_sources[0x7b]	380871	1		T1	43		T2	1266		T3	151
valid_sources[0x7c]	378181	1		T1	51		T2	479		T3	165
valid_sources[0x7d]	1310576	1		T1	45		T2	995		T3	168
valid_sources[0x7e]	377534	1		T1	40		T2	1477		T3	188
valid_sources[0x7f]	382925	1		T1	43		T2	404		T3	139
valid_sources[0x80]	735083	1		T1	60		T2	204		T3	216

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64815604

1

T1

5938

T2

123476

T3

22554

values[0x0]

all_enables

biggest_size

521406

1

T1

10

T2

15

T3

20

values[0x1]

all_enables

biggest_size

520883

1

T1

8

T2

13

T3

14