Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1792855	0	0
cfg0_rd_A	2147483647	2163	0	0
compare_lower0_0_rd_A	2147483647	2154	0	0
compare_upper0_0_rd_A	2147483647	1919	0	0
ctrl_rd_A	2147483647	1897	0	0
intr_enable0_rd_A	2147483647	3252	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1792855	0	0
T12	138511	43365	0	0
T13	860690	0	0	0
T14	536799	0	0	0
T15	0	481766	0	0
T16	0	59459	0	0
T37	0	86387	0	0
T38	0	123513	0	0
T39	0	114006	0	0
T40	0	275011	0	0
T41	0	52559	0	0
T42	0	32168	0	0
T43	0	123546	0	0
T44	385852	0	0	0
T45	329685	0	0	0
T46	181446	0	0	0
T47	104063	0	0	0
T48	665936	0	0	0
T49	525677	0	0	0
T50	613240	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2163	0	0
T34	0	63	0	0
T37	310712	435	0	0
T51	0	16	0	0
T52	0	16	0	0
T53	0	16	0	0
T54	0	20	0	0
T55	0	9	0	0
T56	0	17	0	0
T57	0	233	0	0
T58	0	194	0	0
T59	194496	0	0	0
T60	152329	0	0	0
T61	183440	0	0	0
T62	844679	0	0	0
T63	136179	0	0	0
T64	149989	0	0	0
T65	103856	0	0	0
T66	879535	0	0	0
T67	242209	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2154	0	0
T34	0	15	0	0
T37	310712	513	0	0
T51	0	23	0	0
T52	0	38	0	0
T53	0	11	0	0
T54	0	4	0	0
T55	0	6	0	0
T56	0	17	0	0
T57	0	212	0	0
T58	0	136	0	0
T59	194496	0	0	0
T60	152329	0	0	0
T61	183440	0	0	0
T62	844679	0	0	0
T63	136179	0	0	0
T64	149989	0	0	0
T65	103856	0	0	0
T66	879535	0	0	0
T67	242209	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1919	0	0
T34	0	34	0	0
T37	310712	447	0	0
T51	0	25	0	0
T52	0	31	0	0
T53	0	9	0	0
T54	0	10	0	0
T55	0	7	0	0
T56	0	2	0	0
T57	0	222	0	0
T59	194496	0	0	0
T60	152329	0	0	0
T61	183440	0	0	0
T62	844679	0	0	0
T63	136179	0	0	0
T64	149989	0	0	0
T65	103856	0	0	0
T66	879535	0	0	0
T67	242209	0	0	0
T68	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1897	0	0
T34	0	17	0	0
T37	310712	416	0	0
T51	0	17	0	0
T52	0	33	0	0
T53	0	17	0	0
T54	0	13	0	0
T55	0	5	0	0
T56	0	23	0	0
T57	0	201	0	0
T59	194496	0	0	0
T60	152329	0	0	0
T61	183440	0	0	0
T62	844679	0	0	0
T63	136179	0	0	0
T64	149989	0	0	0
T65	103856	0	0	0
T66	879535	0	0	0
T67	242209	0	0	0
T68	0	7	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3252	0	0
T6	2812	43	0	0
T7	399175	0	0	0
T8	114152	0	0	0
T9	132881	0	0	0
T10	432033	0	0	0
T11	216868	0	0	0
T12	138511	0	0	0
T13	860690	0	0	0
T37	0	611	0	0
T44	385852	0	0	0
T47	0	64	0	0
T61	0	22	0	0
T69	0	95	0	0
T70	0	37	0	0
T71	0	17	0	0
T72	0	87	0	0
T73	0	30	0	0
T74	0	109	0	0
T75	109404	0	0	0