Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56520931	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	58451580	1		T1	671776		T2	8576		T3	47

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	113309871	1		T1	134565		T2	16915		T3	59
values[0x0]	790032	1		T1	22		T2	9		T3	34
values[0x1]	872608	1		T1	15		T2	11		T3	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45121731	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	69850780	1		T1	806986		T2	10232		T3	49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	359917	1		T1	5148		T4	2813		T7	325
valid_sources[0x01]	356686	1		T1	5337		T4	2794		T7	286
valid_sources[0x02]	358476	1		T1	5232		T4	2641		T7	320
valid_sources[0x03]	359012	1		T1	5263		T4	2756		T7	229
valid_sources[0x04]	358892	1		T1	5266		T4	2701		T7	308
valid_sources[0x05]	356196	1		T1	5179		T4	2812		T7	261
valid_sources[0x06]	426234	1		T1	5254		T4	2786		T7	270
valid_sources[0x07]	715360	1		T1	5336		T4	2719		T7	302
valid_sources[0x08]	793571	1		T1	5249		T4	2727		T7	257
valid_sources[0x09]	361668	1		T1	5404		T4	2775		T7	272
valid_sources[0x0a]	357188	1		T1	5263		T4	2816		T7	252
valid_sources[0x0b]	360290	1		T1	5308		T4	2568		T7	300
valid_sources[0x0c]	358366	1		T1	5156		T4	2952		T7	273
valid_sources[0x0d]	357006	1		T1	5282		T4	2700		T7	285
valid_sources[0x0e]	356403	1		T1	5344		T4	2787		T7	303
valid_sources[0x0f]	420392	1		T1	5272		T3	3		T4	2670
valid_sources[0x10]	357075	1		T1	5261		T4	2904		T7	273
valid_sources[0x11]	358346	1		T1	5248		T4	2713		T7	226
valid_sources[0x12]	358621	1		T1	5310		T4	2847		T7	357
valid_sources[0x13]	1186204	1		T1	5177		T4	2645		T7	340
valid_sources[0x14]	354625	1		T1	5247		T4	2868		T7	277
valid_sources[0x15]	357953	1		T1	5237		T4	2661		T7	255
valid_sources[0x16]	357309	1		T1	5135		T4	2653		T7	299
valid_sources[0x17]	359549	1		T1	5219		T4	2884		T7	322
valid_sources[0x18]	358730	1		T1	5336		T4	2728		T7	227
valid_sources[0x19]	495886	1		T1	5218		T4	2671		T7	290
valid_sources[0x1a]	355842	1		T1	5321		T4	2665		T7	301
valid_sources[0x1b]	406946	1		T1	5164		T4	2832		T7	307
valid_sources[0x1c]	585959	1		T1	5282		T4	2816		T7	282
valid_sources[0x1d]	359016	1		T1	5249		T4	2775		T7	264
valid_sources[0x1e]	356379	1		T1	5480		T4	2704		T7	269
valid_sources[0x1f]	359474	1		T1	5249		T3	1		T4	2708
valid_sources[0x20]	355352	1		T1	5232		T4	2705		T7	255
valid_sources[0x21]	356751	1		T1	5215		T4	2784		T7	271
valid_sources[0x22]	360711	1		T1	5073		T4	2869		T7	317
valid_sources[0x23]	356906	1		T1	5082		T4	2825		T7	306
valid_sources[0x24]	685062	1		T1	5151		T4	2768		T7	283
valid_sources[0x25]	357746	1		T1	5226		T3	3		T4	2780
valid_sources[0x26]	367715	1		T1	5280		T3	3		T4	2790
valid_sources[0x27]	354387	1		T1	5298		T3	9		T4	2881
valid_sources[0x28]	843801	1		T1	5306		T4	2735		T7	309
valid_sources[0x29]	359165	1		T1	5225		T4	2783		T7	221
valid_sources[0x2a]	358515	1		T1	5222		T4	2790		T7	262
valid_sources[0x2b]	365207	1		T1	5289		T4	2859		T7	253
valid_sources[0x2c]	358030	1		T1	5102		T3	12		T4	2777
valid_sources[0x2d]	357886	1		T1	5457		T4	2692		T7	296
valid_sources[0x2e]	359729	1		T1	5138		T4	2652		T7	371
valid_sources[0x2f]	354971	1		T1	5244		T4	2797		T7	311
valid_sources[0x30]	357809	1		T1	5323		T4	2747		T7	272
valid_sources[0x31]	1677193	1		T1	5338		T4	2872		T7	282
valid_sources[0x32]	357525	1		T1	5302		T4	2703		T7	316
valid_sources[0x33]	359860	1		T1	5229		T4	2587		T7	245
valid_sources[0x34]	356550	1		T1	5323		T4	2721		T7	283
valid_sources[0x35]	360028	1		T1	5409		T4	2978		T7	271
valid_sources[0x36]	356201	1		T1	5294		T4	2737		T7	184
valid_sources[0x37]	1296602	1		T1	5093		T4	2725		T7	260
valid_sources[0x38]	358075	1		T1	5321		T4	2678		T7	297
valid_sources[0x39]	358891	1		T1	5302		T4	2745		T7	252
valid_sources[0x3a]	359474	1		T1	5418		T4	2684		T7	294
valid_sources[0x3b]	361881	1		T1	5207		T4	2765		T7	241
valid_sources[0x3c]	393957	1		T1	5256		T4	2736		T7	332
valid_sources[0x3d]	360285	1		T1	5260		T4	2829		T7	308
valid_sources[0x3e]	360405	1		T1	5419		T4	2816		T7	297
valid_sources[0x3f]	357831	1		T1	5229		T4	2767		T7	277
valid_sources[0x40]	366350	1		T1	5281		T3	1		T4	2870
valid_sources[0x41]	364153	1		T1	5076		T4	2789		T7	265
valid_sources[0x42]	359493	1		T1	5418		T4	2751		T7	215
valid_sources[0x43]	358421	1		T1	5325		T4	2761		T7	311
valid_sources[0x44]	357484	1		T1	5267		T4	2794		T7	300
valid_sources[0x45]	371528	1		T1	5268		T4	2876		T7	287
valid_sources[0x46]	381718	1		T1	5193		T4	2629		T7	291
valid_sources[0x47]	355879	1		T1	5340		T4	2790		T7	281
valid_sources[0x48]	360233	1		T1	5322		T4	2878		T7	332
valid_sources[0x49]	357827	1		T1	5075		T4	2729		T7	260
valid_sources[0x4a]	476151	1		T1	5345		T4	2798		T7	294
valid_sources[0x4b]	356335	1		T1	5165		T4	2735		T7	284
valid_sources[0x4c]	357902	1		T1	5186		T3	1		T4	2769
valid_sources[0x4d]	374151	1		T1	5251		T4	2859		T7	287
valid_sources[0x4e]	539868	1		T1	5194		T3	1		T4	2719
valid_sources[0x4f]	356265	1		T1	5119		T4	2607		T7	291
valid_sources[0x50]	358549	1		T1	5310		T4	2805		T7	281
valid_sources[0x51]	358273	1		T1	5152		T4	2689		T7	285
valid_sources[0x52]	419055	1		T1	5067		T4	2744		T7	216
valid_sources[0x53]	359104	1		T1	5403		T4	2672		T7	243
valid_sources[0x54]	357777	1		T1	5416		T4	2739		T7	332
valid_sources[0x55]	357272	1		T1	5245		T3	4		T4	2675
valid_sources[0x56]	357457	1		T1	5130		T4	2720		T7	264
valid_sources[0x57]	361628	1		T1	5488		T4	2815		T7	255
valid_sources[0x58]	354435	1		T1	5322		T4	2799		T7	239
valid_sources[0x59]	1118085	1		T1	5106		T4	2871		T7	263
valid_sources[0x5a]	891949	1		T1	5262		T4	2798		T7	220
valid_sources[0x5b]	356504	1		T1	5280		T3	2		T4	2738
valid_sources[0x5c]	357096	1		T1	5276		T3	8		T4	2853
valid_sources[0x5d]	519576	1		T1	5199		T3	3		T4	2908
valid_sources[0x5e]	357376	1		T1	5237		T4	2722		T7	294
valid_sources[0x5f]	359226	1		T1	5241		T4	2783		T7	331
valid_sources[0x60]	412868	1		T1	5189		T4	2772		T7	342
valid_sources[0x61]	360590	1		T1	5216		T4	2765		T7	273
valid_sources[0x62]	358617	1		T1	5307		T4	2691		T7	241
valid_sources[0x63]	357906	1		T1	5326		T4	2796		T7	268
valid_sources[0x64]	423003	1		T1	5206		T3	6		T4	2808
valid_sources[0x65]	357910	1		T1	5242		T4	2830		T7	315
valid_sources[0x66]	424971	1		T1	5299		T4	2621		T7	251
valid_sources[0x67]	827311	1		T1	5153		T4	2828		T7	294
valid_sources[0x68]	356463	1		T1	5236		T4	2838		T7	246
valid_sources[0x69]	354454	1		T1	5062		T4	2883		T7	299
valid_sources[0x6a]	357560	1		T1	5261		T4	2787		T7	291
valid_sources[0x6b]	357338	1		T1	5286		T4	2746		T7	295
valid_sources[0x6c]	431179	1		T1	5197		T4	2712		T7	241
valid_sources[0x6d]	709956	1		T1	5187		T4	2692		T7	255
valid_sources[0x6e]	357239	1		T1	5259		T4	2876		T7	295
valid_sources[0x6f]	357233	1		T1	5191		T4	2810		T7	282
valid_sources[0x70]	356175	1		T1	5213		T4	2899		T7	288
valid_sources[0x71]	357285	1		T1	5267		T4	2656		T7	216
valid_sources[0x72]	394532	1		T1	5108		T4	2836		T7	253
valid_sources[0x73]	355531	1		T1	5373		T4	2747		T7	313
valid_sources[0x74]	359367	1		T1	5150		T4	2838		T7	294
valid_sources[0x75]	441257	1		T1	5302		T4	2794		T7	223
valid_sources[0x76]	358718	1		T1	5155		T4	2835		T7	276
valid_sources[0x77]	356926	1		T1	5355		T4	2775		T7	248
valid_sources[0x78]	356592	1		T1	5176		T3	2		T4	2668
valid_sources[0x79]	358833	1		T1	5281		T4	2651		T7	330
valid_sources[0x7a]	356879	1		T1	5227		T4	2693		T7	269
valid_sources[0x7b]	1506885	1		T1	5272		T4	2628		T7	282
valid_sources[0x7c]	358388	1		T1	5339		T4	2845		T7	265
valid_sources[0x7d]	356635	1		T1	5242		T4	2673		T7	263
valid_sources[0x7e]	356100	1		T1	5373		T4	2580		T7	308
valid_sources[0x7f]	611410	1		T1	5299		T4	2694		T7	245
valid_sources[0x80]	357961	1		T1	5174		T4	2926		T7	260

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

56899739

1

T1

671753

T2

8561

T3

34

values[0x0]

all_enables

biggest_size

776637

1

T1

14

T2

7

T3

9

values[0x1]

all_enables

biggest_size

775204

1

T1

9

T2

8

T3

4