Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2722801	0	0
cfg0_rd_A	2147483647	4351	0	0
compare_lower0_0_rd_A	2147483647	4226	0	0
compare_upper0_0_rd_A	2147483647	3681	0	0
ctrl_rd_A	2147483647	3875	0	0
intr_enable0_rd_A	2147483647	4982	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2722801	0	0
T11	703300	214774	0	0
T12	0	215465	0	0
T13	0	447855	0	0
T33	474654	0	0	0
T34	0	164396	0	0
T35	0	59848	0	0
T36	0	160644	0	0
T37	0	67138	0	0
T38	0	40066	0	0
T39	0	215158	0	0
T40	0	337708	0	0
T41	208065	0	0	0
T42	279918	0	0	0
T43	130450	0	0	0
T44	985872	0	0	0
T45	6591	0	0	0
T46	204850	0	0	0
T47	179940	0	0	0
T48	588390	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4351	0	0
T29	0	138	0	0
T34	825435	1711	0	0
T38	0	498	0	0
T49	0	265	0	0
T50	0	389	0	0
T51	0	231	0	0
T52	0	21	0	0
T53	0	60	0	0
T54	0	90	0	0
T55	0	9	0	0
T56	175364	0	0	0
T57	111696	0	0	0
T58	404444	0	0	0
T59	358816	0	0	0
T60	807267	0	0	0
T61	689053	0	0	0
T62	823655	0	0	0
T63	858114	0	0	0
T64	385328	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4226	0	0
T29	0	90	0	0
T34	825435	1898	0	0
T38	0	409	0	0
T49	0	243	0	0
T50	0	458	0	0
T51	0	216	0	0
T52	0	6	0	0
T53	0	36	0	0
T54	0	55	0	0
T55	0	9	0	0
T56	175364	0	0	0
T57	111696	0	0	0
T58	404444	0	0	0
T59	358816	0	0	0
T60	807267	0	0	0
T61	689053	0	0	0
T62	823655	0	0	0
T63	858114	0	0	0
T64	385328	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3681	0	0
T29	0	69	0	0
T34	825435	1520	0	0
T38	0	378	0	0
T49	0	245	0	0
T50	0	323	0	0
T51	0	254	0	0
T52	0	22	0	0
T53	0	63	0	0
T54	0	37	0	0
T55	0	11	0	0
T56	175364	0	0	0
T57	111696	0	0	0
T58	404444	0	0	0
T59	358816	0	0	0
T60	807267	0	0	0
T61	689053	0	0	0
T62	823655	0	0	0
T63	858114	0	0	0
T64	385328	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3875	0	0
T29	0	79	0	0
T34	825435	1611	0	0
T38	0	480	0	0
T49	0	304	0	0
T50	0	365	0	0
T51	0	220	0	0
T52	0	15	0	0
T53	0	34	0	0
T54	0	45	0	0
T56	175364	0	0	0
T57	111696	0	0	0
T58	404444	0	0	0
T59	358816	0	0	0
T60	807267	0	0	0
T61	689053	0	0	0
T62	823655	0	0	0
T63	858114	0	0	0
T64	385328	0	0	0
T65	0	52	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4982	0	0
T3	3575	70	0	0
T4	855556	0	0	0
T5	166868	0	0	0
T6	589783	0	0	0
T7	305970	0	0	0
T8	123189	0	0	0
T9	464259	0	0	0
T10	669093	0	0	0
T33	0	14	0	0
T34	0	1862	0	0
T38	0	484	0	0
T49	0	341	0	0
T50	0	463	0	0
T66	0	17	0	0
T67	0	12	0	0
T68	0	25	0	0
T69	0	66	0	0
T70	769129	0	0	0
T71	270732	0	0	0