ae68723071| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 44.131m | 85.911ms | 198 | 200 | 99.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 14.875us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.650s | 23.758us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.220s | 119.658us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.870s | 44.339us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.450s | 115.826us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.650s | 23.758us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.870s | 44.339us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 253 | 255 | 99.22 | |||
| V2 | random_reset | rv_timer_random_reset | 31.536m | 92.208ms | 48 | 50 | 96.00 |
| V2 | disabled | rv_timer_disabled | 7.402m | 1.000s | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 24.665m | 2.527s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 24.665m | 2.527s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.313h | 1.685s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.600s | 16.128us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.010s | 1.164ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.010s | 1.164ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 14.875us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 23.758us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.870s | 44.339us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.880s | 161.772us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 14.875us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 23.758us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.870s | 44.339us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.880s | 161.772us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 290 | 97.93 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.890s | 93.345us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.410s | 434.847us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.410s | 434.847us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 22.399m | 43.792ms | 15 | 50 | 30.00 |
| V3 | TOTAL | 15 | 50 | 30.00 | |||
| TOTAL | 577 | 620 | 93.06 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.59 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.43 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
0.rv_timer_stress_all_with_rand_reset.48829587381837296915251957922395608719425513452866987721671387169637445507871
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 480416424 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 480416424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.67025288856817183702339546890235065520053244807094758211777222181064829795753
Line 954, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 288574109887 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10024 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 288574109887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
Test rv_timer_random_reset has 2 failures.
2.rv_timer_random_reset.60672877298489658101307712561396154310951838143385328786313269907179894355058
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.rv_timer_random_reset.79733087413792796285936434470923718182183779343914718392454419840271544751534
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_disabled has 4 failures.
3.rv_timer_disabled.67470770339703705756407348240980391080041158441374687126247728576763850661777
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_timer_disabled.105675720888743585501808147284915515913779142052417726204193259608163267170764
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
20.rv_timer_random.31882810732155190496409601603896773819695651533849136624718528263545445567170
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_random/latest/run.log
Job ID: smart:a4e4afbc-1f06-4f6f-a35d-69e8931d94f5
113.rv_timer_random.14821876046680306404448356695258152354577515177054128597174215904778059159108
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/113.rv_timer_random/latest/run.log
Job ID: smart:249ba65a-78ce-4461-a9b5-9072887a8d25
UVM_ERROR (cip_base_vseq.sv:753) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
10.rv_timer_stress_all_with_rand_reset.7602432391557310614831802511889658983695957362802889600690031979186860133113
Line 948, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/10.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 504693741685 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 504693741685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---