Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2519282	0	0
cfg0_rd_A	2147483647	4321	0	0
compare_lower0_0_rd_A	2147483647	4793	0	0
compare_upper0_0_rd_A	2147483647	3935	0	0
ctrl_rd_A	2147483647	4293	0	0
intr_enable0_rd_A	2147483647	5819	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2519282	0	0
T12	725343	204324	0	0
T13	118429	0	0	0
T14	138947	0	0	0
T15	0	58846	0	0
T16	0	226122	0	0
T36	355944	0	0	0
T37	0	344048	0	0
T38	0	417284	0	0
T39	0	162618	0	0
T40	0	196584	0	0
T41	0	70060	0	0
T42	0	329114	0	0
T43	0	51476	0	0
T44	162027	0	0	0
T45	438178	0	0	0
T46	526119	0	0	0
T47	499918	0	0	0
T48	409134	0	0	0
T49	117115	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4321	0	0
T12	725343	1071	0	0
T13	118429	0	0	0
T14	138947	0	0	0
T30	0	49	0	0
T33	0	424	0	0
T36	355944	0	0	0
T41	0	807	0	0
T43	0	409	0	0
T44	162027	0	0	0
T45	438178	0	0	0
T46	526119	0	0	0
T47	499918	0	0	0
T48	409134	0	0	0
T49	117115	0	0	0
T50	0	357	0	0
T51	0	3	0	0
T52	0	6	0	0
T53	0	34	0	0
T54	0	9	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4793	0	0
T12	725343	1299	0	0
T13	118429	0	0	0
T14	138947	0	0	0
T30	0	42	0	0
T33	0	447	0	0
T36	355944	0	0	0
T41	0	932	0	0
T43	0	682	0	0
T44	162027	0	0	0
T45	438178	0	0	0
T46	526119	0	0	0
T47	499918	0	0	0
T48	409134	0	0	0
T49	117115	0	0	0
T50	0	391	0	0
T51	0	6	0	0
T52	0	6	0	0
T53	0	53	0	0
T55	0	50	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3935	0	0
T12	725343	1130	0	0
T13	118429	0	0	0
T14	138947	0	0	0
T30	0	40	0	0
T33	0	454	0	0
T36	355944	0	0	0
T41	0	671	0	0
T43	0	471	0	0
T44	162027	0	0	0
T45	438178	0	0	0
T46	526119	0	0	0
T47	499918	0	0	0
T48	409134	0	0	0
T49	117115	0	0	0
T50	0	323	0	0
T53	0	20	0	0
T55	0	32	0	0
T56	0	7	0	0
T57	0	80	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4293	0	0
T12	725343	1169	0	0
T13	118429	0	0	0
T14	138947	0	0	0
T30	0	44	0	0
T33	0	471	0	0
T36	355944	0	0	0
T41	0	796	0	0
T43	0	540	0	0
T44	162027	0	0	0
T45	438178	0	0	0
T46	526119	0	0	0
T47	499918	0	0	0
T48	409134	0	0	0
T49	117115	0	0	0
T50	0	282	0	0
T51	0	11	0	0
T53	0	36	0	0
T54	0	3	0	0
T55	0	29	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5819	0	0
T12	725343	1480	0	0
T13	118429	0	0	0
T14	138947	0	0	0
T36	355944	0	0	0
T41	0	832	0	0
T43	0	788	0	0
T44	162027	0	0	0
T45	438178	0	0	0
T46	526119	0	0	0
T47	499918	0	0	0
T48	409134	0	0	0
T49	117115	0	0	0
T58	0	46	0	0
T59	0	18	0	0
T60	0	83	0	0
T61	0	65	0	0
T62	0	31	0	0
T63	0	48	0	0
T64	0	19	0	0