Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71120662	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	73209786	1		T1	105968		T2	33		T3	8514

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142537190	1		T1	211816		T2	58		T3	17057
values[0x0]	852621	1		T1	162		T2	5		T3	31
values[0x1]	940637	1		T1	138		T2	1		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56781910	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	87548538	1		T1	127161		T2	38		T3	10217

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	459415	1		T1	8139		T3	58		T5	335
valid_sources[0x01]	456604	1		T1	8601		T3	67		T5	378
valid_sources[0x02]	468711	1		T1	8517		T3	65		T5	334
valid_sources[0x03]	460836	1		T1	8021		T3	76		T5	355
valid_sources[0x04]	458498	1		T1	8281		T2	2		T3	60
valid_sources[0x05]	460575	1		T1	8472		T3	63		T5	373
valid_sources[0x06]	457713	1		T1	8247		T3	62		T5	364
valid_sources[0x07]	478052	1		T1	8502		T3	77		T5	360
valid_sources[0x08]	462724	1		T1	8312		T3	62		T5	356
valid_sources[0x09]	458816	1		T1	8349		T3	65		T5	332
valid_sources[0x0a]	817494	1		T1	8667		T3	70		T5	349
valid_sources[0x0b]	504567	1		T1	8498		T3	70		T5	378
valid_sources[0x0c]	458517	1		T1	8066		T3	55		T5	323
valid_sources[0x0d]	464454	1		T1	8660		T3	54		T5	326
valid_sources[0x0e]	460294	1		T1	8108		T3	58		T5	375
valid_sources[0x0f]	459202	1		T1	8272		T3	59		T5	373
valid_sources[0x10]	456610	1		T1	7834		T3	67		T5	341
valid_sources[0x11]	459623	1		T1	8468		T3	68		T5	373
valid_sources[0x12]	705149	1		T1	8287		T3	76		T5	338
valid_sources[0x13]	457253	1		T1	8502		T3	66		T5	343
valid_sources[0x14]	458568	1		T1	8363		T3	62		T5	371
valid_sources[0x15]	518890	1		T1	8079		T3	82		T5	367
valid_sources[0x16]	747530	1		T1	8344		T3	60		T5	362
valid_sources[0x17]	461963	1		T1	8401		T2	2		T3	71
valid_sources[0x18]	457119	1		T1	8315		T3	66		T5	361
valid_sources[0x19]	459093	1		T1	8245		T3	78		T5	294
valid_sources[0x1a]	461832	1		T1	8252		T2	1		T3	75
valid_sources[0x1b]	479950	1		T1	8286		T2	3		T3	60
valid_sources[0x1c]	459561	1		T1	8474		T3	73		T5	382
valid_sources[0x1d]	471565	1		T1	8103		T3	60		T5	338
valid_sources[0x1e]	506027	1		T1	8546		T3	64		T5	355
valid_sources[0x1f]	458727	1		T1	8161		T3	62		T5	376
valid_sources[0x20]	654433	1		T1	7996		T2	3		T3	80
valid_sources[0x21]	459392	1		T1	8168		T3	54		T5	339
valid_sources[0x22]	461181	1		T1	8415		T3	78		T5	387
valid_sources[0x23]	500922	1		T1	8525		T2	1		T3	61
valid_sources[0x24]	460454	1		T1	8284		T3	50		T5	359
valid_sources[0x25]	459168	1		T1	8318		T3	69		T5	395
valid_sources[0x26]	460004	1		T1	8112		T3	60		T5	380
valid_sources[0x27]	480078	1		T1	8004		T3	83		T5	350
valid_sources[0x28]	458690	1		T1	8393		T3	68		T5	353
valid_sources[0x29]	460094	1		T1	8173		T2	3		T3	59
valid_sources[0x2a]	471185	1		T1	8712		T3	69		T5	314
valid_sources[0x2b]	463133	1		T1	7812		T3	71		T5	392
valid_sources[0x2c]	457542	1		T1	8178		T3	59		T4	1
valid_sources[0x2d]	921696	1		T1	7990		T3	70		T5	371
valid_sources[0x2e]	458708	1		T1	7953		T3	88		T5	375
valid_sources[0x2f]	464766	1		T1	8429		T2	1		T3	79
valid_sources[0x30]	458432	1		T1	8163		T3	69		T5	344
valid_sources[0x31]	459284	1		T1	8300		T3	70		T5	348
valid_sources[0x32]	457464	1		T1	8434		T3	59		T5	360
valid_sources[0x33]	463740	1		T1	8499		T3	71		T5	346
valid_sources[0x34]	459659	1		T1	8708		T2	1		T3	62
valid_sources[0x35]	458589	1		T1	8364		T3	61		T4	1
valid_sources[0x36]	1034653	1		T1	8652		T3	73		T5	355
valid_sources[0x37]	456689	1		T1	8223		T3	59		T5	327
valid_sources[0x38]	462500	1		T1	8036		T3	61		T5	330
valid_sources[0x39]	457952	1		T1	8204		T3	73		T5	353
valid_sources[0x3a]	460509	1		T1	8138		T3	62		T5	384
valid_sources[0x3b]	724666	1		T1	8162		T3	66		T5	349
valid_sources[0x3c]	458539	1		T1	8445		T3	71		T5	357
valid_sources[0x3d]	648827	1		T1	8015		T3	64		T4	2
valid_sources[0x3e]	461470	1		T1	8366		T3	65		T5	356
valid_sources[0x3f]	665257	1		T1	7875		T3	63		T5	361
valid_sources[0x40]	456993	1		T1	7592		T3	67		T5	351
valid_sources[0x41]	458539	1		T1	8293		T3	56		T5	346
valid_sources[0x42]	462388	1		T1	8228		T3	74		T5	383
valid_sources[0x43]	458866	1		T1	8284		T3	57		T5	376
valid_sources[0x44]	460812	1		T1	8369		T3	66		T5	355
valid_sources[0x45]	456596	1		T1	7808		T2	2		T3	69
valid_sources[0x46]	458236	1		T1	8483		T3	77		T5	388
valid_sources[0x47]	457514	1		T1	8422		T3	63		T5	348
valid_sources[0x48]	467036	1		T1	8367		T3	63		T5	362
valid_sources[0x49]	458324	1		T1	8248		T3	64		T4	1
valid_sources[0x4a]	460532	1		T1	8344		T3	68		T5	376
valid_sources[0x4b]	462899	1		T1	8184		T3	80		T5	384
valid_sources[0x4c]	459083	1		T1	8249		T3	61		T5	326
valid_sources[0x4d]	475901	1		T1	8202		T2	2		T3	57
valid_sources[0x4e]	457759	1		T1	8061		T3	56		T5	338
valid_sources[0x4f]	458893	1		T1	8346		T3	69		T5	350
valid_sources[0x50]	457131	1		T1	8537		T2	4		T3	90
valid_sources[0x51]	458003	1		T1	8124		T3	58		T5	345
valid_sources[0x52]	460711	1		T1	8557		T3	86		T5	352
valid_sources[0x53]	462700	1		T1	8270		T3	55		T5	391
valid_sources[0x54]	458301	1		T1	8570		T2	2		T3	57
valid_sources[0x55]	457308	1		T1	8444		T3	85		T5	359
valid_sources[0x56]	456552	1		T1	8078		T3	46		T5	324
valid_sources[0x57]	458126	1		T1	8241		T3	66		T5	352
valid_sources[0x58]	460268	1		T1	8352		T3	79		T5	338
valid_sources[0x59]	744565	1		T1	7980		T3	57		T5	359
valid_sources[0x5a]	597584	1		T1	8285		T3	60		T4	1
valid_sources[0x5b]	460051	1		T1	8274		T2	4		T3	52
valid_sources[0x5c]	495243	1		T1	8383		T3	78		T5	395
valid_sources[0x5d]	1065073	1		T1	8619		T3	70		T5	348
valid_sources[0x5e]	464160	1		T1	8595		T3	72		T5	382
valid_sources[0x5f]	903893	1		T1	8272		T3	71		T5	347
valid_sources[0x60]	459349	1		T1	8465		T3	59		T5	385
valid_sources[0x61]	463734	1		T1	8170		T3	64		T5	371
valid_sources[0x62]	1504262	1		T1	8384		T3	62		T5	371
valid_sources[0x63]	456738	1		T1	8690		T3	51		T5	367
valid_sources[0x64]	458680	1		T1	8623		T3	86		T5	366
valid_sources[0x65]	458639	1		T1	8571		T3	84		T5	359
valid_sources[0x66]	492106	1		T1	8335		T3	66		T5	344
valid_sources[0x67]	457451	1		T1	8042		T3	58		T5	373
valid_sources[0x68]	459900	1		T1	8399		T3	68		T4	1
valid_sources[0x69]	487992	1		T1	8583		T3	62		T5	383
valid_sources[0x6a]	459885	1		T1	8208		T3	77		T5	368
valid_sources[0x6b]	459211	1		T1	8281		T2	1		T3	60
valid_sources[0x6c]	1457197	1		T1	8346		T2	2		T3	63
valid_sources[0x6d]	479920	1		T1	8444		T3	82		T5	368
valid_sources[0x6e]	462251	1		T1	8541		T3	72		T5	369
valid_sources[0x6f]	459043	1		T1	8148		T3	75		T5	347
valid_sources[0x70]	663909	1		T1	8194		T3	61		T5	378
valid_sources[0x71]	576949	1		T1	7980		T2	1		T3	64
valid_sources[0x72]	458046	1		T1	8170		T3	64		T5	362
valid_sources[0x73]	457007	1		T1	8213		T2	3		T3	62
valid_sources[0x74]	458361	1		T1	8258		T3	51		T5	334
valid_sources[0x75]	462190	1		T1	8251		T3	63		T5	348
valid_sources[0x76]	460148	1		T1	8189		T3	80		T5	380
valid_sources[0x77]	458312	1		T1	8410		T3	69		T5	325
valid_sources[0x78]	456015	1		T1	8067		T3	61		T4	1
valid_sources[0x79]	461538	1		T1	8325		T3	51		T5	350
valid_sources[0x7a]	462218	1		T1	8407		T3	77		T5	393
valid_sources[0x7b]	509505	1		T1	8593		T3	53		T5	365
valid_sources[0x7c]	458123	1		T1	8164		T3	67		T5	344
valid_sources[0x7d]	458488	1		T1	7801		T3	78		T5	347
valid_sources[0x7e]	461927	1		T1	8540		T3	49		T5	365
valid_sources[0x7f]	461036	1		T1	8343		T3	58		T5	349
valid_sources[0x80]	458248	1		T1	8171		T3	50		T5	367

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71535976

1

T1

105945

T2

28

T3

8475

values[0x0]

all_enables

biggest_size

837882

1

T1

133

T2

4

T3

21

values[0x1]

all_enables

biggest_size

835928

1

T1

94

T2

1

T3

18