Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2919928	0	0
cfg0_rd_A	2147483647	9440	0	0
compare_lower0_0_rd_A	2147483647	10317	0	0
compare_upper0_0_rd_A	2147483647	9012	0	0
ctrl_rd_A	2147483647	9514	0	0
intr_enable0_rd_A	2147483647	10766	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2919928	0	0
T11	777990	190669	0	0
T12	143709	371030	0	0
T13	0	56470	0	0
T34	0	126533	0	0
T35	0	81074	0	0
T36	0	224489	0	0
T37	0	170692	0	0
T38	0	148121	0	0
T39	0	227964	0	0
T40	0	285488	0	0
T41	123957	0	0	0
T42	139719	0	0	0
T43	275890	0	0	0
T44	168130	0	0	0
T45	174711	0	0	0
T46	217704	0	0	0
T47	356847	0	0	0
T48	136111	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9440	0	0
T12	143709	3628	0	0
T13	0	373	0	0
T31	0	21	0	0
T36	0	1232	0	0
T38	0	1577	0	0
T42	139719	0	0	0
T43	275890	0	0	0
T44	168130	0	0	0
T45	174711	0	0	0
T46	217704	0	0	0
T47	356847	0	0	0
T48	136111	0	0	0
T49	0	313	0	0
T50	0	9	0	0
T51	0	8	0	0
T52	0	9	0	0
T53	0	7	0	0
T54	127543	0	0	0
T55	279857	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10317	0	0
T12	143709	4109	0	0
T13	0	413	0	0
T29	0	18	0	0
T31	0	10	0	0
T36	0	1564	0	0
T38	0	1779	0	0
T42	139719	0	0	0
T43	275890	0	0	0
T44	168130	0	0	0
T45	174711	0	0	0
T46	217704	0	0	0
T47	356847	0	0	0
T48	136111	0	0	0
T49	0	580	0	0
T50	0	8	0	0
T51	0	10	0	0
T53	0	1	0	0
T54	127543	0	0	0
T55	279857	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9012	0	0
T12	143709	3707	0	0
T13	0	361	0	0
T29	0	11	0	0
T31	0	21	0	0
T36	0	1234	0	0
T38	0	1412	0	0
T42	139719	0	0	0
T43	275890	0	0	0
T44	168130	0	0	0
T45	174711	0	0	0
T46	217704	0	0	0
T47	356847	0	0	0
T48	136111	0	0	0
T49	0	294	0	0
T50	0	8	0	0
T51	0	8	0	0
T52	0	3	0	0
T54	127543	0	0	0
T55	279857	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9514	0	0
T12	143709	3924	0	0
T13	0	326	0	0
T31	0	15	0	0
T36	0	1271	0	0
T38	0	1547	0	0
T42	139719	0	0	0
T43	275890	0	0	0
T44	168130	0	0	0
T45	174711	0	0	0
T46	217704	0	0	0
T47	356847	0	0	0
T48	136111	0	0	0
T49	0	409	0	0
T50	0	9	0	0
T51	0	12	0	0
T52	0	9	0	0
T53	0	2	0	0
T54	127543	0	0	0
T55	279857	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10766	0	0
T12	143709	4177	0	0
T13	0	319	0	0
T36	0	1502	0	0
T38	0	1921	0	0
T42	139719	0	0	0
T43	275890	0	0	0
T44	168130	0	0	0
T45	174711	0	0	0
T46	217704	0	0	0
T47	356847	0	0	0
T48	136111	0	0	0
T54	127543	0	0	0
T55	279857	0	0	0
T56	0	69	0	0
T57	0	33	0	0
T58	0	10	0	0
T59	0	21	0	0
T60	0	30	0	0
T61	0	62	0	0