Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1286569	0	0
cfg0_rd_A	2147483647	3371	0	0
compare_lower0_0_rd_A	2147483647	3374	0	0
compare_upper0_0_rd_A	2147483647	3197	0	0
ctrl_rd_A	2147483647	2872	0	0
intr_enable0_rd_A	2147483647	4184	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1286569	0	0
T14	206831	53349	0	0
T15	0	34907	0	0
T16	0	154319	0	0
T21	390503	0	0	0
T22	868700	0	0	0
T23	307402	0	0	0
T24	115619	0	0	0
T25	262932	0	0	0
T26	121887	0	0	0
T27	127788	0	0	0
T28	125712	0	0	0
T35	0	155462	0	0
T36	0	61762	0	0
T37	0	38766	0	0
T38	0	326821	0	0
T39	0	98175	0	0
T40	0	52125	0	0
T41	0	90688	0	0
T42	162228	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3371	0	0
T14	206831	627	0	0
T15	0	274	0	0
T21	390503	0	0	0
T22	868700	0	0	0
T23	307402	0	0	0
T24	115619	0	0	0
T25	262932	0	0	0
T26	121887	0	0	0
T27	127788	0	0	0
T28	125712	0	0	0
T31	0	39	0	0
T37	0	144	0	0
T41	0	547	0	0
T42	162228	0	0	0
T43	0	39	0	0
T44	0	10	0	0
T45	0	9	0	0
T46	0	144	0	0
T47	0	118	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3374	0	0
T14	206831	674	0	0
T15	0	475	0	0
T21	390503	0	0	0
T22	868700	0	0	0
T23	307402	0	0	0
T24	115619	0	0	0
T25	262932	0	0	0
T26	121887	0	0	0
T27	127788	0	0	0
T28	125712	0	0	0
T31	0	21	0	0
T37	0	212	0	0
T41	0	605	0	0
T42	162228	0	0	0
T43	0	29	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	70	0	0
T47	0	66	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3197	0	0
T14	206831	537	0	0
T15	0	372	0	0
T21	390503	0	0	0
T22	868700	0	0	0
T23	307402	0	0	0
T24	115619	0	0	0
T25	262932	0	0	0
T26	121887	0	0	0
T27	127788	0	0	0
T28	125712	0	0	0
T31	0	34	0	0
T37	0	246	0	0
T41	0	559	0	0
T42	162228	0	0	0
T43	0	27	0	0
T45	0	9	0	0
T46	0	61	0	0
T47	0	57	0	0
T48	0	126	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2872	0	0
T14	206831	476	0	0
T15	0	333	0	0
T21	390503	0	0	0
T22	868700	0	0	0
T23	307402	0	0	0
T24	115619	0	0	0
T25	262932	0	0	0
T26	121887	0	0	0
T27	127788	0	0	0
T28	125712	0	0	0
T31	0	27	0	0
T37	0	236	0	0
T41	0	437	0	0
T42	162228	0	0	0
T43	0	43	0	0
T44	0	10	0	0
T45	0	2	0	0
T46	0	77	0	0
T47	0	74	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4184	0	0
T14	206831	650	0	0
T15	0	471	0	0
T21	390503	0	0	0
T22	868700	0	0	0
T23	307402	0	0	0
T24	115619	0	0	0
T25	262932	0	0	0
T26	121887	0	0	0
T27	127788	0	0	0
T28	125712	0	0	0
T42	162228	0	0	0
T49	0	65	0	0
T50	0	24	0	0
T51	0	58	0	0
T52	0	22	0	0
T53	0	30	0	0
T54	0	38	0	0
T55	0	15	0	0
T56	0	69	0	0