Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59557218	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	61382900	1		T1	1531		T2	107007		T3	61771

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	119389776	1		T1	2980		T2	213818		T3	123380
values[0x0]	736660	1		T1	10		T2	21		T3	20
values[0x1]	813682	1		T1	11		T2	20		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47547193	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	73392925	1		T1	1817		T2	128473		T3	74193

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	337000	1		T1	8		T4	103		T6	282
valid_sources[0x01]	336012	1		T1	8		T4	144		T6	299
valid_sources[0x02]	333751	1		T1	8		T4	147		T6	315
valid_sources[0x03]	711148	1		T1	13		T4	138		T6	305
valid_sources[0x04]	566970	1		T1	14		T4	153		T6	289
valid_sources[0x05]	335554	1		T1	16		T4	121		T6	310
valid_sources[0x06]	338582	1		T1	6		T4	135		T6	252
valid_sources[0x07]	358665	1		T1	15		T4	116		T6	271
valid_sources[0x08]	339273	1		T1	10		T4	149		T6	271
valid_sources[0x09]	339063	1		T1	19		T4	159		T6	258
valid_sources[0x0a]	1622073	1		T1	4		T4	153		T6	264
valid_sources[0x0b]	337742	1		T1	9		T4	137		T6	285
valid_sources[0x0c]	373559	1		T1	4		T4	125		T6	228
valid_sources[0x0d]	333420	1		T1	18		T4	102		T6	290
valid_sources[0x0e]	362114	1		T1	24		T4	152		T6	294
valid_sources[0x0f]	336525	1		T1	17		T4	144		T6	267
valid_sources[0x10]	349418	1		T1	10		T4	149		T6	310
valid_sources[0x11]	337046	1		T1	15		T4	144		T6	305
valid_sources[0x12]	401678	1		T1	7		T4	120		T6	301
valid_sources[0x13]	336425	1		T1	16		T4	127		T6	259
valid_sources[0x14]	338899	1		T1	7		T4	155		T6	251
valid_sources[0x15]	338364	1		T1	15		T4	122		T6	286
valid_sources[0x16]	411751	1		T1	15		T4	99		T6	290
valid_sources[0x17]	757483	1		T1	10		T4	140		T6	282
valid_sources[0x18]	341569	1		T1	6		T4	142		T6	246
valid_sources[0x19]	337048	1		T1	13		T4	146		T6	265
valid_sources[0x1a]	364735	1		T1	17		T4	137		T6	291
valid_sources[0x1b]	334795	1		T1	18		T4	105		T6	310
valid_sources[0x1c]	338507	1		T1	16		T4	126		T6	249
valid_sources[0x1d]	339484	1		T1	9		T4	139		T6	267
valid_sources[0x1e]	360696	1		T1	12		T4	133		T6	298
valid_sources[0x1f]	338584	1		T1	10		T4	130		T6	302
valid_sources[0x20]	334660	1		T1	18		T4	128		T6	289
valid_sources[0x21]	391782	1		T1	8		T4	132		T6	314
valid_sources[0x22]	451138	1		T1	11		T4	131		T6	269
valid_sources[0x23]	338025	1		T1	14		T4	145		T6	283
valid_sources[0x24]	395709	1		T1	9		T4	171		T6	303
valid_sources[0x25]	3342531	1		T1	14		T4	130		T6	258
valid_sources[0x26]	334684	1		T1	15		T4	140		T6	259
valid_sources[0x27]	3933531	1		T1	12		T4	124		T6	254
valid_sources[0x28]	338833	1		T1	14		T4	129		T6	305
valid_sources[0x29]	339851	1		T1	12		T4	137		T6	281
valid_sources[0x2a]	399826	1		T1	8		T4	135		T6	278
valid_sources[0x2b]	605702	1		T1	13		T4	111		T6	278
valid_sources[0x2c]	336516	1		T1	10		T4	135		T6	296
valid_sources[0x2d]	337293	1		T1	26		T4	147		T6	287
valid_sources[0x2e]	338126	1		T1	6		T4	134		T6	263
valid_sources[0x2f]	403717	1		T1	14		T4	152		T6	294
valid_sources[0x30]	336515	1		T1	13		T4	150		T6	278
valid_sources[0x31]	338118	1		T1	10		T4	152		T6	278
valid_sources[0x32]	336048	1		T1	5		T4	123		T6	308
valid_sources[0x33]	338566	1		T1	3		T4	132		T6	278
valid_sources[0x34]	338226	1		T1	14		T4	117		T6	268
valid_sources[0x35]	336555	1		T1	10		T4	139		T6	284
valid_sources[0x36]	533544	1		T1	18		T4	144		T6	292
valid_sources[0x37]	337661	1		T1	10		T4	123		T6	290
valid_sources[0x38]	334168	1		T1	13		T4	92		T6	263
valid_sources[0x39]	334084	1		T1	5		T4	141		T6	307
valid_sources[0x3a]	336191	1		T1	7		T4	155		T6	324
valid_sources[0x3b]	332941	1		T1	18		T4	136		T6	259
valid_sources[0x3c]	337774	1		T1	9		T4	134		T6	293
valid_sources[0x3d]	378983	1		T1	9		T4	119		T6	253
valid_sources[0x3e]	338655	1		T1	5		T4	117		T6	281
valid_sources[0x3f]	336994	1		T1	5		T4	108		T6	275
valid_sources[0x40]	396158	1		T1	15		T4	146		T6	296
valid_sources[0x41]	332472	1		T1	15		T4	169		T6	247
valid_sources[0x42]	703316	1		T1	12		T4	146		T6	276
valid_sources[0x43]	337850	1		T1	9		T4	137		T6	263
valid_sources[0x44]	579916	1		T1	6		T4	113		T6	281
valid_sources[0x45]	334264	1		T1	11		T4	162		T6	290
valid_sources[0x46]	336944	1		T1	9		T4	111		T6	284
valid_sources[0x47]	336284	1		T1	2		T4	151		T6	283
valid_sources[0x48]	338673	1		T1	11		T4	142		T6	226
valid_sources[0x49]	336813	1		T1	10		T4	163		T6	301
valid_sources[0x4a]	384072	1		T1	12		T4	125		T6	295
valid_sources[0x4b]	337762	1		T1	16		T4	112		T6	272
valid_sources[0x4c]	935602	1		T1	17		T4	141		T6	309
valid_sources[0x4d]	338883	1		T1	14		T4	148		T6	268
valid_sources[0x4e]	336259	1		T1	9		T4	134		T6	285
valid_sources[0x4f]	334450	1		T1	12		T4	127		T6	286
valid_sources[0x50]	386397	1		T1	9		T4	121		T6	259
valid_sources[0x51]	336665	1		T1	17		T4	149		T6	255
valid_sources[0x52]	336920	1		T1	14		T4	129		T6	267
valid_sources[0x53]	335842	1		T1	10		T4	135		T6	286
valid_sources[0x54]	338647	1		T1	17		T4	144		T6	287
valid_sources[0x55]	339486	1		T1	9		T4	163		T6	278
valid_sources[0x56]	336074	1		T1	14		T4	123		T6	263
valid_sources[0x57]	335608	1		T1	10		T4	132		T6	263
valid_sources[0x58]	372337	1		T1	11		T4	117		T6	304
valid_sources[0x59]	336770	1		T1	13		T4	133		T6	289
valid_sources[0x5a]	499724	1		T1	8		T4	133		T6	319
valid_sources[0x5b]	335481	1		T1	14		T4	104		T6	238
valid_sources[0x5c]	381244	1		T1	15		T4	126		T6	308
valid_sources[0x5d]	364531	1		T1	10		T4	106		T6	290
valid_sources[0x5e]	858486	1		T1	14		T4	138		T6	299
valid_sources[0x5f]	337810	1		T1	17		T4	121		T6	282
valid_sources[0x60]	338414	1		T1	9		T4	134		T6	273
valid_sources[0x61]	364110	1		T1	7		T4	141		T6	295
valid_sources[0x62]	421379	1		T1	14		T4	120		T6	307
valid_sources[0x63]	345848	1		T1	13		T4	151		T6	262
valid_sources[0x64]	334765	1		T1	14		T4	128		T6	301
valid_sources[0x65]	1738746	1		T1	20		T4	127		T6	278
valid_sources[0x66]	334045	1		T1	12		T4	133		T6	303
valid_sources[0x67]	683428	1		T1	4		T4	130		T6	316
valid_sources[0x68]	338501	1		T1	28		T4	108		T6	279
valid_sources[0x69]	396159	1		T1	12		T4	124		T6	299
valid_sources[0x6a]	1043723	1		T1	8		T4	134		T6	283
valid_sources[0x6b]	336412	1		T1	17		T4	141		T6	277
valid_sources[0x6c]	340315	1		T1	18		T4	113		T6	291
valid_sources[0x6d]	2811886	1		T1	17		T4	137		T6	302
valid_sources[0x6e]	469775	1		T1	15		T4	156		T6	306
valid_sources[0x6f]	334044	1		T1	14		T4	111		T6	288
valid_sources[0x70]	354187	1		T1	8		T4	137		T6	327
valid_sources[0x71]	336619	1		T1	15		T4	153		T6	293
valid_sources[0x72]	338245	1		T1	13		T4	97		T6	255
valid_sources[0x73]	338156	1		T1	11		T4	155		T6	258
valid_sources[0x74]	383835	1		T1	12		T4	107		T6	273
valid_sources[0x75]	1536151	1		T1	9		T4	140		T6	273
valid_sources[0x76]	336489	1		T1	8		T4	164		T6	283
valid_sources[0x77]	333441	1		T1	12		T4	136		T6	271
valid_sources[0x78]	336724	1		T1	8		T4	133		T6	309
valid_sources[0x79]	334280	1		T1	12		T4	151		T6	281
valid_sources[0x7a]	336787	1		T1	11		T4	113		T6	280
valid_sources[0x7b]	335412	1		T1	12		T4	134		T6	283
valid_sources[0x7c]	336000	1		T1	16		T4	146		T6	279
valid_sources[0x7d]	335513	1		T1	2		T4	195		T6	272
valid_sources[0x7e]	336764	1		T1	12		T4	137		T6	287
valid_sources[0x7f]	380297	1		T1	9		T4	127		T6	287
valid_sources[0x80]	334845	1		T1	6		T4	142		T6	266

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59936617

1

T1

1513

T2

107004

T3

61743

values[0x0]

all_enables

biggest_size

723647

1

T1

9

T2

14

T3

17

values[0x1]

all_enables

biggest_size

722636

1

T1

9

T2

15

T3

11