Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2526857	0	0
cfg0_rd_A	2147483647	6278	0	0
compare_lower0_0_rd_A	2147483647	6871	0	0
compare_upper0_0_rd_A	2147483647	6345	0	0
ctrl_rd_A	2147483647	6174	0	0
intr_enable0_rd_A	2147483647	7527	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2526857	0	0
T12	570879	242365	0	0
T13	0	187658	0	0
T14	0	98483	0	0
T20	103496	0	0	0
T27	1964	0	0	0
T29	0	141006	0	0
T30	0	18867	0	0
T31	0	268359	0	0
T32	0	125393	0	0
T33	0	297452	0	0
T34	0	187766	0	0
T35	0	185932	0	0
T36	655227	0	0	0
T37	302379	0	0	0
T38	535438	0	0	0
T39	331500	0	0	0
T40	284796	0	0	0
T41	707176	0	0	0
T42	594734	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6278	0	0
T21	0	99	0	0
T23	0	107	0	0
T24	0	39	0	0
T30	736217	167	0	0
T34	0	1927	0	0
T43	0	1007	0	0
T44	0	1787	0	0
T45	0	203	0	0
T46	0	9	0	0
T47	0	3	0	0
T48	100727	0	0	0
T49	113620	0	0	0
T50	104841	0	0	0
T51	224495	0	0	0
T52	174005	0	0	0
T53	462856	0	0	0
T54	153065	0	0	0
T55	565911	0	0	0
T56	480603	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6871	0	0
T21	0	72	0	0
T23	0	63	0	0
T30	736217	247	0	0
T34	0	2262	0	0
T43	0	1238	0	0
T44	0	1868	0	0
T45	0	258	0	0
T46	0	2	0	0
T48	100727	0	0	0
T49	113620	0	0	0
T50	104841	0	0	0
T51	224495	0	0	0
T52	174005	0	0	0
T53	462856	0	0	0
T54	153065	0	0	0
T55	565911	0	0	0
T56	480603	0	0	0
T57	0	9	0	0
T58	0	9	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6345	0	0
T21	0	72	0	0
T23	0	75	0	0
T24	0	8	0	0
T30	736217	113	0	0
T34	0	2037	0	0
T43	0	1265	0	0
T44	0	1833	0	0
T45	0	222	0	0
T46	0	9	0	0
T47	0	11	0	0
T48	100727	0	0	0
T49	113620	0	0	0
T50	104841	0	0	0
T51	224495	0	0	0
T52	174005	0	0	0
T53	462856	0	0	0
T54	153065	0	0	0
T55	565911	0	0	0
T56	480603	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6174	0	0
T21	0	49	0	0
T23	0	69	0	0
T24	0	45	0	0
T30	736217	238	0	0
T34	0	1841	0	0
T43	0	1277	0	0
T44	0	1630	0	0
T45	0	201	0	0
T46	0	11	0	0
T48	100727	0	0	0
T49	113620	0	0	0
T50	104841	0	0	0
T51	224495	0	0	0
T52	174005	0	0	0
T53	462856	0	0	0
T54	153065	0	0	0
T55	565911	0	0	0
T56	480603	0	0	0
T57	0	25	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7527	0	0
T30	0	207	0	0
T34	0	1976	0	0
T59	258668	105	0	0
T60	0	21	0	0
T61	0	35	0	0
T62	0	54	0	0
T63	0	13	0	0
T64	0	44	0	0
T65	0	72	0	0
T66	0	22	0	0
T67	909262	0	0	0
T68	124646	0	0	0
T69	83700	0	0	0
T70	278891	0	0	0
T71	184499	0	0	0
T72	124363	0	0	0
T73	740469	0	0	0
T74	390416	0	0	0
T75	127644	0	0	0