Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1545358	0	0
cfg0_rd_A	2147483647	5939	0	0
compare_lower0_0_rd_A	2147483647	5703	0	0
compare_upper0_0_rd_A	2147483647	5542	0	0
ctrl_rd_A	2147483647	5325	0	0
intr_enable0_rd_A	2147483647	7169	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1545358	0	0
T7	341710	144099	0	0
T8	513279	0	0	0
T9	231581	0	0	0
T10	288059	0	0	0
T12	0	331156	0	0
T13	0	120790	0	0
T30	0	106	0	0
T32	0	248352	0	0
T33	0	195235	0	0
T34	0	181836	0	0
T35	0	108930	0	0
T36	0	176950	0	0
T37	0	25490	0	0
T38	777108	0	0	0
T39	609141	0	0	0
T40	687572	0	0	0
T41	566342	0	0	0
T42	107750	0	0	0
T43	440329	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5939	0	0
T28	0	57	0	0
T29	0	181	0	0
T30	0	33	0	0
T32	114738	2344	0	0
T36	0	884	0	0
T44	0	20	0	0
T45	0	9	0	0
T46	0	7	0	0
T47	0	4	0	0
T48	0	139	0	0
T49	298611	0	0	0
T50	121163	0	0	0
T51	196885	0	0	0
T52	695153	0	0	0
T53	129909	0	0	0
T54	7645	0	0	0
T55	680045	0	0	0
T56	237139	0	0	0
T57	156114	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5703	0	0
T28	0	49	0	0
T29	0	117	0	0
T30	0	24	0	0
T32	114738	2618	0	0
T36	0	934	0	0
T44	0	26	0	0
T45	0	12	0	0
T47	0	1	0	0
T48	0	54	0	0
T49	298611	0	0	0
T50	121163	0	0	0
T51	196885	0	0	0
T52	695153	0	0	0
T53	129909	0	0	0
T54	7645	0	0	0
T55	680045	0	0	0
T56	237139	0	0	0
T57	156114	0	0	0
T58	0	4	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5542	0	0
T28	0	33	0	0
T29	0	76	0	0
T30	0	34	0	0
T32	114738	2543	0	0
T36	0	894	0	0
T44	0	21	0	0
T45	0	8	0	0
T46	0	1	0	0
T48	0	71	0	0
T49	298611	0	0	0
T50	121163	0	0	0
T51	196885	0	0	0
T52	695153	0	0	0
T53	129909	0	0	0
T54	7645	0	0	0
T55	680045	0	0	0
T56	237139	0	0	0
T57	156114	0	0	0
T58	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5325	0	0
T28	0	28	0	0
T29	0	82	0	0
T30	0	23	0	0
T32	114738	2373	0	0
T36	0	877	0	0
T44	0	14	0	0
T45	0	7	0	0
T46	0	1	0	0
T47	0	9	0	0
T48	0	83	0	0
T49	298611	0	0	0
T50	121163	0	0	0
T51	196885	0	0	0
T52	695153	0	0	0
T53	129909	0	0	0
T54	7645	0	0	0
T55	680045	0	0	0
T56	237139	0	0	0
T57	156114	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7169	0	0
T26	0	42	0	0
T32	0	3032	0	0
T59	999167	76	0	0
T60	392097	53	0	0
T61	0	6	0	0
T62	0	131	0	0
T63	0	14	0	0
T64	0	30	0	0
T65	0	26	0	0
T66	0	69	0	0
T67	105791	0	0	0
T68	906660	0	0	0
T69	127073	0	0	0
T70	438987	0	0	0
T71	386761	0	0	0
T72	181149	0	0	0
T73	872130	0	0	0
T74	663056	0	0	0