Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	69385224	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	70642946	1		T1	7327		T2	10668		T3	40817

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138942572	1		T1	14397		T2	21243		T3	81844
values[0x0]	515523	1		T1	20		T2	8		T3	17
values[0x1]	570075	1		T1	23		T2	2		T3	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55423698	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	84604472	1		T1	8797		T2	12818		T3	48912

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	349912	1		T1	50		T3	315		T5	2
valid_sources[0x01]	380182	1		T1	74		T3	314		T5	1
valid_sources[0x02]	391820	1		T1	27		T3	315		T5	7
valid_sources[0x03]	353178	1		T1	21		T3	332		T5	3
valid_sources[0x04]	350289	1		T1	72		T3	309		T5	2
valid_sources[0x05]	351823	1		T1	78		T3	308		T5	8
valid_sources[0x06]	349354	1		T1	46		T3	307		T6	168
valid_sources[0x07]	349541	1		T1	63		T3	315		T5	3
valid_sources[0x08]	352051	1		T1	92		T3	318		T5	2
valid_sources[0x09]	757656	1		T1	22		T3	306		T5	2
valid_sources[0x0a]	351536	1		T1	53		T3	313		T6	93
valid_sources[0x0b]	353250	1		T1	53		T3	325		T5	2
valid_sources[0x0c]	350264	1		T1	58		T3	342		T5	1
valid_sources[0x0d]	642039	1		T1	31		T3	299		T5	6
valid_sources[0x0e]	3781904	1		T1	77		T3	310		T6	150
valid_sources[0x0f]	347526	1		T1	48		T3	316		T5	6
valid_sources[0x10]	351541	1		T1	60		T3	340		T5	6
valid_sources[0x11]	350358	1		T1	63		T3	294		T5	7
valid_sources[0x12]	350818	1		T1	64		T3	300		T5	10
valid_sources[0x13]	367528	1		T1	31		T3	297		T5	1
valid_sources[0x14]	353147	1		T1	53		T3	375		T5	6
valid_sources[0x15]	350195	1		T1	54		T3	319		T5	9
valid_sources[0x16]	350150	1		T1	54		T3	341		T5	10
valid_sources[0x17]	443927	1		T1	41		T3	328		T5	6
valid_sources[0x18]	381942	1		T1	94		T3	326		T5	5
valid_sources[0x19]	617977	1		T1	30		T3	350		T5	2
valid_sources[0x1a]	438490	1		T1	59		T3	348		T5	3
valid_sources[0x1b]	348759	1		T1	46		T3	356		T5	6
valid_sources[0x1c]	446673	1		T1	80		T3	342		T5	5
valid_sources[0x1d]	355130	1		T1	67		T3	325		T5	2
valid_sources[0x1e]	349968	1		T1	50		T3	318		T5	4
valid_sources[0x1f]	349533	1		T1	64		T3	304		T5	12
valid_sources[0x20]	346789	1		T1	56		T3	369		T5	7
valid_sources[0x21]	430895	1		T1	99		T3	328		T5	7
valid_sources[0x22]	348470	1		T1	40		T3	343		T5	5
valid_sources[0x23]	382621	1		T1	34		T3	289		T5	7
valid_sources[0x24]	349908	1		T1	74		T3	336		T5	6
valid_sources[0x25]	350473	1		T1	23		T3	317		T5	14
valid_sources[0x26]	349588	1		T1	56		T3	320		T5	5
valid_sources[0x27]	576635	1		T1	80		T3	341		T5	6
valid_sources[0x28]	349490	1		T1	65		T3	331		T5	1
valid_sources[0x29]	371055	1		T1	41		T3	282		T5	5
valid_sources[0x2a]	352684	1		T1	78		T3	300		T6	63
valid_sources[0x2b]	350485	1		T1	112		T3	307		T5	3
valid_sources[0x2c]	917437	1		T1	70		T3	320		T5	6
valid_sources[0x2d]	482468	1		T1	44		T3	285		T5	3
valid_sources[0x2e]	349456	1		T1	87		T3	296		T5	4
valid_sources[0x2f]	9244878	1		T1	80		T3	291		T5	4
valid_sources[0x30]	345901	1		T1	39		T3	304		T5	1
valid_sources[0x31]	2372096	1		T1	67		T3	325		T5	4
valid_sources[0x32]	352885	1		T1	84		T3	338		T5	6
valid_sources[0x33]	1032162	1		T1	95		T3	311		T6	207
valid_sources[0x34]	353127	1		T1	75		T3	325		T5	2
valid_sources[0x35]	345837	1		T1	30		T3	335		T6	48
valid_sources[0x36]	352021	1		T1	67		T3	318		T6	102
valid_sources[0x37]	347930	1		T1	45		T3	324		T6	103
valid_sources[0x38]	369371	1		T1	91		T3	317		T5	6
valid_sources[0x39]	351025	1		T1	56		T3	312		T5	7
valid_sources[0x3a]	752974	1		T1	49		T3	334		T5	3
valid_sources[0x3b]	443277	1		T1	42		T3	338		T5	4
valid_sources[0x3c]	350785	1		T1	22		T3	321		T5	4
valid_sources[0x3d]	351343	1		T1	104		T3	331		T5	3
valid_sources[0x3e]	349957	1		T1	77		T3	320		T6	185
valid_sources[0x3f]	893036	1		T1	93		T3	361		T5	3
valid_sources[0x40]	351083	1		T1	73		T3	339		T5	3
valid_sources[0x41]	352034	1		T1	84		T3	318		T5	11
valid_sources[0x42]	351410	1		T1	15		T3	324		T5	7
valid_sources[0x43]	352619	1		T1	48		T3	327		T5	2
valid_sources[0x44]	351553	1		T1	48		T3	323		T6	116
valid_sources[0x45]	351681	1		T1	80		T3	291		T5	7
valid_sources[0x46]	351519	1		T1	40		T3	323		T5	9
valid_sources[0x47]	349847	1		T1	39		T3	338		T5	2
valid_sources[0x48]	352359	1		T1	52		T3	311		T5	5
valid_sources[0x49]	347669	1		T1	24		T3	322		T5	5
valid_sources[0x4a]	350527	1		T1	49		T3	319		T5	3
valid_sources[0x4b]	748673	1		T1	38		T3	319		T5	6
valid_sources[0x4c]	350030	1		T1	61		T3	283		T5	2
valid_sources[0x4d]	356774	1		T1	48		T3	327		T5	1
valid_sources[0x4e]	351640	1		T1	82		T3	343		T5	7
valid_sources[0x4f]	350231	1		T1	19		T3	341		T5	11
valid_sources[0x50]	352068	1		T1	55		T3	292		T6	115
valid_sources[0x51]	353586	1		T1	37		T3	290		T5	3
valid_sources[0x52]	350128	1		T1	73		T3	297		T5	6
valid_sources[0x53]	405124	1		T1	49		T3	302		T5	2
valid_sources[0x54]	349950	1		T1	27		T3	366		T5	3
valid_sources[0x55]	348607	1		T1	45		T3	316		T5	4
valid_sources[0x56]	350965	1		T1	30		T3	353		T5	2
valid_sources[0x57]	348164	1		T1	62		T3	289		T5	9
valid_sources[0x58]	400269	1		T1	101		T3	303		T5	1
valid_sources[0x59]	369524	1		T1	64		T3	317		T5	4
valid_sources[0x5a]	353206	1		T1	49		T3	288		T5	7
valid_sources[0x5b]	360142	1		T1	64		T3	272		T5	3
valid_sources[0x5c]	349690	1		T1	32		T3	298		T5	3
valid_sources[0x5d]	352810	1		T1	59		T3	362		T5	5
valid_sources[0x5e]	683741	1		T1	70		T3	328		T5	12
valid_sources[0x5f]	350864	1		T1	55		T3	353		T5	4
valid_sources[0x60]	375244	1		T1	49		T3	303		T6	71
valid_sources[0x61]	349750	1		T1	36		T3	306		T5	13
valid_sources[0x62]	352785	1		T1	95		T3	340		T5	6
valid_sources[0x63]	350371	1		T1	30		T3	283		T5	5
valid_sources[0x64]	348633	1		T1	58		T3	299		T5	2
valid_sources[0x65]	354507	1		T1	38		T3	309		T5	6
valid_sources[0x66]	363031	1		T1	31		T3	290		T5	4
valid_sources[0x67]	348794	1		T1	59		T3	328		T5	11
valid_sources[0x68]	349259	1		T1	28		T3	356		T5	4
valid_sources[0x69]	1240756	1		T1	60		T3	321		T5	3
valid_sources[0x6a]	352893	1		T1	40		T3	290		T5	2
valid_sources[0x6b]	380072	1		T1	36		T3	275		T5	7
valid_sources[0x6c]	348843	1		T1	92		T3	306		T5	4
valid_sources[0x6d]	362344	1		T1	101		T3	267		T5	3
valid_sources[0x6e]	347082	1		T1	37		T3	369		T5	11
valid_sources[0x6f]	410459	1		T1	79		T3	287		T5	9
valid_sources[0x70]	351203	1		T1	33		T3	320		T5	3
valid_sources[0x71]	362386	1		T1	53		T3	300		T5	12
valid_sources[0x72]	350800	1		T1	18		T3	311		T5	7
valid_sources[0x73]	352707	1		T1	43		T3	338		T5	3
valid_sources[0x74]	351626	1		T1	25		T3	316		T5	2
valid_sources[0x75]	352342	1		T1	42		T3	315		T5	2
valid_sources[0x76]	2415745	1		T1	56		T3	329		T5	4
valid_sources[0x77]	350316	1		T1	76		T3	299		T5	4
valid_sources[0x78]	352751	1		T1	61		T3	308		T5	2
valid_sources[0x79]	348591	1		T1	42		T3	308		T5	4
valid_sources[0x7a]	350274	1		T1	20		T3	352		T5	1
valid_sources[0x7b]	351510	1		T1	78		T3	301		T6	105
valid_sources[0x7c]	348566	1		T1	20		T3	344		T5	16
valid_sources[0x7d]	348999	1		T1	88		T3	345		T5	3
valid_sources[0x7e]	352539	1		T1	49		T3	316		T6	97
valid_sources[0x7f]	350898	1		T1	80		T3	337		T5	6
valid_sources[0x80]	351267	1		T1	104		T3	317		T6	80

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69632909

1

T1

7290

T2

10663

T3

40781

values[0x0]

all_enables

biggest_size

505206

1

T1

19

T2

4

T3

14

values[0x1]

all_enables

biggest_size

504831

1

T1

18

T2

1

T3

22