Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1760208	0	0
cfg0_rd_A	2147483647	5149	0	0
compare_lower0_0_rd_A	2147483647	4934	0	0
compare_upper0_0_rd_A	2147483647	5020	0	0
ctrl_rd_A	2147483647	4771	0	0
intr_enable0_rd_A	2147483647	5739	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1760208	0	0
T16	712123	215544	0	0
T17	812065	170056	0	0
T18	0	35728	0	0
T40	0	160866	0	0
T41	0	74542	0	0
T42	0	296194	0	0
T43	0	510887	0	0
T44	0	115638	0	0
T45	0	29770	0	0
T46	0	88767	0	0
T47	132223	0	0	0
T48	124727	0	0	0
T49	831543	0	0	0
T50	107056	0	0	0
T51	226328	0	0	0
T52	122361	0	0	0
T53	218765	0	0	0
T54	672696	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5149	0	0
T17	812065	1783	0	0
T18	0	367	0	0
T45	0	347	0	0
T50	107056	0	0	0
T51	226328	0	0	0
T52	122361	0	0	0
T53	218765	0	0	0
T54	672696	0	0	0
T55	0	50	0	0
T56	0	42	0	0
T57	0	8	0	0
T58	0	5	0	0
T59	0	28	0	0
T60	0	20	0	0
T61	0	5	0	0
T62	348745	0	0	0
T63	213622	0	0	0
T64	262852	0	0	0
T65	110289	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4934	0	0
T17	812065	1690	0	0
T18	0	458	0	0
T45	0	317	0	0
T50	107056	0	0	0
T51	226328	0	0	0
T52	122361	0	0	0
T53	218765	0	0	0
T54	672696	0	0	0
T55	0	57	0	0
T56	0	6	0	0
T57	0	3	0	0
T58	0	16	0	0
T59	0	51	0	0
T60	0	4	0	0
T62	348745	0	0	0
T63	213622	0	0	0
T64	262852	0	0	0
T65	110289	0	0	0
T66	0	15	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5020	0	0
T17	812065	1791	0	0
T18	0	392	0	0
T45	0	359	0	0
T50	107056	0	0	0
T51	226328	0	0	0
T52	122361	0	0	0
T53	218765	0	0	0
T54	672696	0	0	0
T55	0	28	0	0
T56	0	13	0	0
T57	0	6	0	0
T58	0	9	0	0
T59	0	30	0	0
T60	0	7	0	0
T62	348745	0	0	0
T63	213622	0	0	0
T64	262852	0	0	0
T65	110289	0	0	0
T66	0	7	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4771	0	0
T17	812065	1589	0	0
T18	0	401	0	0
T45	0	336	0	0
T50	107056	0	0	0
T51	226328	0	0	0
T52	122361	0	0	0
T53	218765	0	0	0
T54	672696	0	0	0
T55	0	36	0	0
T56	0	28	0	0
T57	0	8	0	0
T58	0	5	0	0
T59	0	7	0	0
T60	0	10	0	0
T62	348745	0	0	0
T63	213622	0	0	0
T64	262852	0	0	0
T65	110289	0	0	0
T66	0	9	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5739	0	0
T17	812065	1864	0	0
T18	0	449	0	0
T26	0	4	0	0
T31	0	4	0	0
T45	0	497	0	0
T50	107056	0	0	0
T51	226328	0	0	0
T52	122361	0	0	0
T53	218765	0	0	0
T54	672696	0	0	0
T62	348745	0	0	0
T63	213622	0	0	0
T64	262852	0	0	0
T65	110289	0	0	0
T67	0	49	0	0
T68	0	4	0	0
T69	0	13	0	0
T70	0	16	0	0
T71	0	61	0	0